ST STM32L0x3 User Manual

RM0367 Rev 7 299/1043
RM0367 Extended interrupt and event controller (EXTI)
301
13.5.4 Falling edge trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
Note: The configurable wakeup lines are edge triggered, no glitch must be generated on these
lines.
If a falling edge on the configurable interrupt line occurs while writing to the EXTI_FTSR
register, the pending bit will not be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
13.5.5 EXTI software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 Res. FT17 FT16
rw rw rw rw rw rw
1514131211109 8765432 1 0
FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
0: Falling trigger disabled (for Event and Interrupt) for input line x
1: Falling trigger enabled (for Event and Interrupt) for input line x
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line x
1: Falling trigger enabled (for Event and Interrupt) for input line x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI22SWI21SWI20SWI19 Res. SWI17 SWI16
rw rw rw rw rw rw
1514131211109 8 765432 1 0
SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English