RM0367 Rev 7 1021/1043
RM0367 Revision history
1039
Revision history
Table 181. Document revision history
Date Revision Changes
11-Feb-2014 1 Initial release.
29-Apr-2014 2
TSC, RNG, ASE and communication sections reordered.
System and memory overview
Updated Section 2.3: Embedded SRAM and Section 2.4: Boot
configuration.
Flash memory/data EEPROM
Updated Figure 6: RDP levels.
Modified Section 3.4.2: PcROP (Proprietary Code Read-Out
Protection).
FIREWALL
Renamed EEPROM PROG, PROG EEPROM, PROG or PROGRAM
MEMORY into Flash program memory.
PWR
Added note 3 related to VREF+ below Section Figure 10.: Power
supply overview.
Updated Section 6.1.1: Independent A/D and DAC converter supply
and reference voltage.
RCC
Updated Figure 16: Simplified diagram of the reset circuit and Figure
17: Clock tree.
Updated Section 7.2.4: HSI48 clock.
Changed MCOSEL[2:0] into MCOSEL[3:0], Section 7.2.14: Clock-out
capability definition updated in Section 7.3.4: Clock configuration
register (RCC_CFGR).
Renamed TOUCHRST into TSCRST in Section 7.3.9: AHB peripheral
reset register (RCC_AHBRSTR). Renamed TOUCHSMEM into
TSCSMEM in Section 7.3.17: AHB peripheral clock enable in Sleep
mode register (RCC_AHBSMENR). Renamed HSI48MSEL into
HSI48SEL in Section 7.3.20: Clock configuration register
(RCC_CCIPR).
SYSCFG:
Updated Section 10.1: Introduction
Renamed REF_CTRL register (Section 10.2.3) into REF_CFGR3 and
changed ENBUFLP_BGAP_COMP to ENBUF_VREFINT_COMP,
ENBUF_BGAP_ADC to ENBUF_VREFINT_ADC,
ENBUF_SENSOR_ADC to ENBUF_TSENSE_ADC.EN_BGAP to
EN_VREFINT and description updated.
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