RM0367 Rev 7 57/1043
RM0367 System and memory overview
57
2.1.1 S0: Cortex
®
-bus
This bus connects the DCode/ICode bus of the Cortex
®
-M0+ core to the BusMatrix. This
bus is used by the core to fetch instructions, get data and access the AHB/APB resources.
2.1.2 S1: DMA-bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of the different masters to Flash memory and data EEPROM, the SRAM and the
AHB/APB peripherals.
2.1.3 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and three
slaves (NVM interface, SRAM, AHB2APB1/2 bridges).
AHB/APB bridges
The AHB/APB bridge provide full synchronous connections between the AHB and the 2
APB buses. APB1 and APB2 operate at a maximum frequency of 32 MHz.
Refer to Section 2.2.2: Memory map and register boundary addresses on page 59 for the
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
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