RM0367 Rev 7 517/1043
RM0367 General-purpose timers (TIM2/TIM3)
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For example, Timer x can be configured to act as a prescaler for Timer y. Refer to
Figure 146. To do this, follow the sequence below:
1. Configure Timer x in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIMx_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
2. To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in
slave mode using ITR1 as internal trigger. This is selected through the TS bits in the
TIMy_SMCR register (writing TS=000).
3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in
the TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the
periodic Timer x trigger signal (which correspond to the timer x counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
For code example, refer to A.11.17: Timer prescaling another timer code example.
Note: If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer y.
Using one timer to enable another timer
In this example, we control the enable of Timer y with the output compare 1 of Timer x.
Refer to Figure 146 for connections. Timer y counts on the divided internal clock only when
OC1REF of Timer x is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (f
CK_CNT
= f
CK_INT
/3).
1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMx_CR2 register).
2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).
3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).
5. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register).
6. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
For code example, refer to A.11.18: Timer enabling another timer code example.
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer y
counter enable signal.