ST STM32L0x3 User Manual

RM0367 Rev 7 213/1043
RM0367 Reset and clock control (RCC)
225
7.3.17 AHB peripheral clock enable in Sleep mode
register (RCC_AHBSMENR)
Address: 0x40
Reset value: the bits corresponding to the available peripherals are set
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
CRYP
SMEN
Res. Res. Res.
RNGS
MEN
Res. Res. Res.
TSCSM
EN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res.
CRC
SMEN
Res. Res.
SRAM
SMEN
MIF
SMEN
Res. Res. Res. Res. Res. Res. Res.
DMA
SMEN
rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 CRYPSMEN: Crypto clock enable during Sleep mode bit
This bit is set and reset by software.
0: Crypto clock disabled in Sleep mode
1: Crypto clock enabled in Sleep mode
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RNGSMEN: Random Number Generator clock enable during Sleep mode bit
This bit is set and reset by software.
0: RNG clock disabled in Sleep mode
1: RNG clock enabled in Sleep mode (if enabled by RNGEN)
Bits 19:17 Reserved, must be kept at reset value.
Bit 16
TSCSMEN: Touch Sensing clock enable during Sleep mode bit
This bit is set and reset by software.
0: Touch Sensing clock disabled in Sleep mode
1: Touch sensing clock enabled in Sleep mode (if enabled by TSCEN)
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during Sleep mode bit
This bit is set and reset by software.
0: Test integration module clock disabled in Sleep mode
1: Test integration module clock enabled in Sleep mode (if enabled by CRCEN)
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAMSMEN: SRAM interface clock enable during Sleep mode bit
This bit is set and reset by software.
0: NVM interface clock disabled in Sleep mode
1: NVM interface clock enabled in Sleep mode

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English