AES hardware accelerator (AES) RM0367
456/1043 RM0367 Rev 7
DMA single requests are generated by AES until it is disabled. So, after the data output
phase at the end of processing of a 128-bit data block, AES switches automatically to a new
data input phase for the next data block, if any.
When the data transferring between AES and memory is managed by DMA, the CCF flag is
not relevant and can be ignored (left set) by software. It must only be cleared when
transiting back to data transferring managed by software. See Suspend/resume operations
in ECB/CBC modes in Section 19.4.8: AES basic chaining modes (ECB, CBC) as example.
19.4.14 AES error management
The read error flag (RDERR) and write error flag (WRERR) of the AES_SR register are set
when an unexpected read or write operation, respectively, is detected. An interrupt can be
generated if the error interrupt enable (ERRIE) bit of the AES_CR register is set. For more
details, refer to Section 19.5: AES interrupts.
Note: AES is not disabled after an error detection and continues processing.
AES can be re-initialized at any moment by clearing then setting the EN bit of the AES_CR
register.
Read error flag (RDERR)
When an unexpected read operation is detected during the computation phase or during the
input phase, the AES read error flag (RDERR) is set in the AES_SR register. An interrupt is
generated if the ERRIE bit of the AES_CR register is set.
The RDERR flag is cleared by setting the corresponding ERRC bit of the AES_CR register.
Write error flag (WDERR)
When an unexpected write operation is detected during the computation phase or during the
output phase, the AES write error flag (WRERR) is set in the AES_SR register. An interrupt
is generated if the ERRIE bit of the AES_CR register is set.
The WDERR flag is cleared by setting the corresponding ERRC bit of the AES_CR register.
19.5 AES interrupts
There are three individual maskable interrupt sources generated by the AES peripheral, to
signal the following events:
• computation completed
• read error, see Section 19.4.14
• write error, see Section 19.4.14
These three sources are combined into a common interrupt signal aes_it that connects to
NVIC (nested vectored interrupt controller).
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