ST STM32L0x3 User Manual

RM0367 Rev 7 207/1043
RM0367 Reset and clock control (RCC)
225
7.3.14 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x34
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG
EN
Res. Res. Res. Res. Res. Res.
rw
1514131211109 8 7 6 543210
Res.
USART1
EN
Res.
SPI1
EN
Res. Res.
ADC
EN
Res. FWEN Res.
TIM22
EN
Res. Res.
TIM21
EN
Res.
SYSCF
EN
rw rw rw rs rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGEN: DBG clock enable bit
This bit is set and cleared by software.
0: DBG clock disabled
1: DBG clock enabled
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable bit
This bit is set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable bit
This bit is set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCEN: ADC clock enable bit
This bit is set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bit 8 Reserved, must be kept at reset value.
Bit 7 FWEN: Firewall clock enable bit
This bit is set by software and reset by hardware. Software can only program this bit to 1.
Writing 0 has not effect.
0: Firewall disabled
1: Firewall clock enabled

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English