Reset and clock control (RCC) RM0367
208/1043 RM0367 Rev 7
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM22EN: TIM22 timer clock enable bit
This bit is set and cleared by software.
0:TIM22 clock disabled
1: TIM22 clock enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21EN: TIM21 timer clock enable bit
This bit is set and cleared by software.
0: TIM21 clock disabled
1: TIM21 clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: System configuration controller clock enable bit
This bit is set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
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