RM0367 Rev 7 575/1043
RM0367 General-purpose timers (TIM21/22)
601
Figure 183. Clearing TIMx OCxREF
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
22.3.11 One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be as follows:
CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
MS33105V1
(CCRx)
Counter (CNT)
ETRF
OCxREF
(OCxCE = ‘0’)
OCxREF
(OCxCE = ‘1’)
OCxREF_CLR
becomes high
OCxREF_CLR
still high
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