ST STM32L0x3 User Manual

RM0367 Rev 7 293/1043
RM0367 Extended interrupt and event controller (EXTI)
301
For the configurable lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.
Note: The interrupts or events associated to the direct lines are triggered only when the system is
in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI.
13.3.1 EXTI block diagram
The block diagram is shown in Figure 29.
Figure 29. Extended interrupts and events controller (EXTI) block diagram
13.3.2 Wakeup event management
The STM32L0x3 microcontrollers are able to handle external or internal events in order to
wake up the core (WFE). The wakeup event can be generated by either:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex
®
-M0+ system control register (see STM32L0 Series
Cortex
®
-M0+ programming manual (PM0223)). When the MCU resumes from WFE,
the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in
the NVIC interrupt clear pending register) have to be cleared.
• or configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not
necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel
pending bit as the pending bit corresponding to the event line is not set.
MSv32798V1
APB bus
Peripheral interface
Edge detect
circuit
PCLK
Interrupts
Software
interrupt
event
register
Rising
trigger
selection
register
Pending
request
register
Interrupt
mask
register
Falling
trigger
selection
register
Event
mask
register
Rising
edge
detect.
Stop mode
Direct
events
Configurable
events
Events
Wakeup

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English