RM0367 Rev 7 209/1043
RM0367 Reset and clock control (RCC)
225
7.3.15 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x38
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
EN
I2C3E
N
DACE
N
PWRE
N
CRSE
N
Res. Res. Res. USBEN
I2C2E
N
I2C1E
N
USART5
EN
USART4
EN
LPUART1
EN
USART2
EN
Res.
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SPI2E
N
Res. Res.
WWDG
EN
Res. LCDEN Res. Res. Res.
TIM7E
N
TIM6EN Res. Res. TIM3EN
TIM2E
N
rw rw rw rw rw rw rw
Bit 31 LPTIM1EN: Low-power timer clock enable bit
This bit is set and cleared by software.
0: Low-power timer clock disabled
1: Low-power timer clock enabled
Bit 30 I2C3EN: I2C3 clock enable bit
This bit is set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 29 DACEN: DAC interface clock enable bit
This bit is set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enabled
Bit 28 PWREN: Power interface clock enable bit
This bit is set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bit 27 CRSEN: Clock recovery system clock enable bit
This bit is set and cleared by software.
0: Clock recovery system clock disabled
1: Clock recovery system clock enabled
Bits 26:24 Reserved, must be kept at reset value.
Bit 23 USBEN: USB clock enable bit
This bit is set and cleared by software.
0: USB clock disabled
1: USB clock enabled
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