Reset and clock control (RCC) RM0367
210/1043 RM0367 Rev 7
Bit 22 I2C2EN: I2C2 clock enable bit
This bit is set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable bit
This bit is set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 USART5EN: USART5 clock enable bit
This bit is set and cleared by software.
0: USART5 clock disabled
1: USART5 clock enabled
Bit 19 USART4EN: USART4 clock enable bit
This bit is set and cleared by software.
0: USART4 clock disabled
1: USART4 clock enabled
Bit 18 LPUART1EN: LPUART1 clock enable bit
This bit is set and cleared by software.
0: LPUART1 clock disabled
1: LPUART1 clock enabled
Bit 17 USART2EN: USART2 clock enable bit
This bit is set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2EN: SPI2 clock enable bit
This bit is set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable bit
This bit is set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 Reserved, must be kept at reset value.
Bit 9 LCDEN: LCD clock enable bit
This bit is set and cleared by software.
0: LCD clock disabled
1: LCD clock enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: Timer 7 clock enable bit
Set and cleared by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled