ST STM32L0x3 User Manual

RM0367 Rev 7 297/1043
RM0367 Extended interrupt and event controller (EXTI)
301
13.5 EXTI registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
13.5.1 EXTI interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x3F84 0000
13.5.2 EXTI event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IM29 IM28 Res. IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 Res. IM17 IM16
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 IMx: Interrupt mask on line x (x = 29 to 28)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 27 Reserved, must be kept at reset value.
Bits 26:19 IMx: Interrupt mask on line x (x = 26 to 19)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 IMx: Interrupt mask on line x (x = 17 to 0)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. EM29 EM28 Res. EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 Res. EM17 EM16
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English