ST STM32L0x3 User Manual

RM0367 Rev 7 201/1043
RM0367 Reset and clock control (RCC)
225
7.3.11 APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 14 USART1RST: USART1 reset
This bit is set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI 1 reset
This bit is set and cleared by software.
0: No effect
1: Reset SPI 1
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC interface reset
This bit is set and cleared by software.
0: No effect
1: Reset ADC interface
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM22RST: TIM22 timer reset
This bit is set and cleared by software.
0: No effect
1: Reset TIM22 timer
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21RST: TIM21 timer reset
This bit is set and cleared by software.
0: No effect
1: Reset TIM21 timer
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: System configuration controller reset
This bit is set and cleared by software.
0: No effect
1: Reset System configuration controller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
RST
I2C3R
ST
DACR
ST
PWR
RST
CRSR
ST
Res. Res. Res. USBRST
I2C2R
ST
I2C1R
ST
USART5
RST
USART4
RST
LPUART1
RST
USART2
RST
Res.
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SPI2R
ST
Res. Res.
WWDG
RST
Res. LCDRST Res. Res. Res.
TIM7R
ST
TIM6RS
T
Res. Res.
TIM3RS
T
TIM2
RST
rw rw rw rw rw rw rw

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English