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RM0367 Rev 7 65/1043

RM0367

The boot mode configuration is latched on the 4th rising edge of SYSCLK after reset. It is up

to the user to set nBOOT1 and BOOT0 to select the required boot mode.

The boot mode configuration is also re-sampled when exiting from Standby mode.

Consequently the boot mode configuration must not be modified in Standby mode. After this

startup delay has elapsed, the CPU fetches the top-of-stack value from address

0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, Flash program memory, system memory or SRAM is

accessible as follows:

• Boot from Flash program memory: the Flash program memory is aliased in the boot

memory space (0x0000 0000), but still accessible from its original memory space

(0x0800 0000). In other words, the Flash memory contents can be accessed starting

from address 0x0000 0000 or 0x0800 0000.

• Boot from system memory: the system memory is aliased in the boot memory space

(0x0000 0000), but still accessible from its original memory space (0x

1FF0 0000).

• Boot from the embedded SRAM: the SRAM is aliased in the boot memory space

(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Bank swapping (category 5 devices only)

For devices featuring two banks, the bank swapping mechanism allows the CPU to point

either to bank1 or to bank 2 in the boot memory space (0x0000 0000). Either Flash program

and data EEPROM address are changed (see Table 8: NVM organization for UFB = 0

(128 Kbyte category 5 devices), Table 10: NVM organization for UFB = 0 (64 Kbyte category

5 devices)).

Physical remap

Once the boot pin and bit are selected, the application software can modify the memory

accessible in the code area. This modification is performed by programming the

MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1).

Embedded bootloader

The embedded bootloader is located in the System memory, programmed by ST during

production. It is used to reprogram the Flash memory using one of the following serial

interfaces:

• For category 3 devices: USART1, USART2, SPI1 or SPI2

• For category 5 devices with USB interface: USART1, USART2 or USB.

• For category 5 devices without USB interface: USART1, USART2, SPI1, SPI2, I2C1 or

I2C2.

For details concerning the bootloader serial interface corresponding I/O, refer to your device

datasheet.

For further details on STM32 bootloader, please refer to AN2606.

ST STM32L0x3 User Manual

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