ST STM32L0x3 User Manual

RM0367 Rev 7 625/1043
RM0367 Low-power timer (LPTIM)
635
The following figure shows a counting sequence for Encoder mode where both-edge
sensitivity is configured.
Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must
be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must
be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’).
Figure 206. Encoder mode counting sequence
24.4.14 Debug mode
When the microcontroller enters debug mode (core halted), the LPTIM counter either
continues to work normally or stops, depending on the DBG_LPTIM_STOP configuration bit
in the DBG module.
24.5 LPTIM low-power modes
MS32491V1
T1
Counter
up updown
T2
Table 111. Effect of low-power modes on the LPTIM
Mode Description
Sleep No effect. LPTIM interrupts cause the device to exit Sleep mode.
Stop
The LPTIM peripheral is active when it is clocked by LSE or LSI. LPTIM
interrupts cause the device to exit Stop mode
Standby
The LPTIM peripheral is powered down and must be reinitialized after
exiting Standby mode.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English