RM0367 Rev 7 519/1043
RM0367 General-purpose timers (TIM2/TIM3)
546
Figure 148. Gating timer y with Enable of timer x
Using one timer to start another timer
In this example, we set the enable of Timer y with the update event of Timer x. Refer to
Figure 146 for connections. Timer y starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer x.
When Timer y receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (f
CK_CNT
= f
CK_INT
/3).
1. Configure Timer x master mode to send its Update Event (UEV) as trigger o
utput
(
MMS=010 in the TIMx_CR2 register).
2. Configure the Timer x period (TIMx_ARR registers).
3. Configure Timer y to get the input trigger from Timer x (TS=000 in the T
IMy_SMCR
re
gister).
4. Configure Timer y in trigger mode (SMS=110 in TIMy_SMCR register).
5.
Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
MS33138V1
CK_INT
75 00
E7
TIMERx-CNT_INIT
TIMERx-CNT
AB
TIMERy-CNT
TIMERy-CNT_INIT
Write TIF = 0
01 02
E9E800
TIMERx-CEN=CNT_EN
TIMERy-write CNT
TIMERy-TIF
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