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Independent watchd
og (IWDG)
RM0367
644/1043
RM0367 Rev 7
25.4.6
IWDG register map
The following table gives the IW
DG register map an
d reset valu
e
s.
Refer to
Section
2.2 on page 58
for the reg
ister boundary addre
sses.
T
able 1
14.
IWDG regis
ter map and re
set values
Offset
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
IWDG_KR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
KEY[15:0]
R
e
s
e
t
v
a
l
u
e
0000000000000000
0x04
IWDG_PR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PR[2:0]
Reset value
000
0x08
IWDG_RLR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RL[1
1:0]
Reset value
111111111111
0x0C
IWDG_SR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WVU
RVU
PVU
Reset value
000
0x10
IWDG_WINR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WIN[1
1:0]
Reset value
111111111111
643
645
Table of Contents
Table of Contents
2
Documentation Conventions
52
General Information
52
List of Abbreviations for Registers
52
Glossary
53
Availability of Peripherals
53
Product Category Definition
53
Table 1. Stm32L0X3 Memory Density
54
Table 2. Overview of Features Per Category
54
System and Memory Overview
56
System Architecture
56
Figure 1. System Architecture
56
S0: Cortex®-Bus
57
S1: DMA-Bus
57
Busmatrix
57
AHB/APB Bridges
57
Memory Organization
58
Introduction
58
Memory Map and Register Boundary Addresses
59
Figure 2. Memory Map
59
Table 3. Stm32L0X3 Peripheral Register Boundary Addresses
60
Embedded SRAM
64
Boot Configuration
64
Table 4. Boot Modes
64
Bank Swapping (Category 5 Devices Only)
65
Physical Remap
65
Embedded Bootloader
65
Flash Program Memory and Data EEPROM (FLASH)
66
Introduction
66
NVM Main Features
66
NVM Functional Description
67
NVM Organization
67
Table 5. NVM Organization (Category 3 Devices)
67
Table 6. NVM Organization for UFB = 0 (192 Kbyte Category 5 Devices)
68
Table 7. Flash Memory and Data EEPROM Remapping (192 Kbyte Category 5 Devices)
69
Table 8. NVM Organization for UFB = 0 (128 Kbyte Category 5 Devices)
69
Table 9. Flash Memory and Data EEPROM Remapping (128 Kbyte Category 5 Devices)
70
Table 10. NVM Organization for UFB = 0 (64 Kbyte Category 5 Devices)
70
Dual-Bank Boot Capability
71
Table 11. Boot Pin and BFB2 Bit Configuration
71
Reading the NVM
72
Protocol to Read
72
Relation between CPU Frequency/Operation Mode/Nvm Read Time
73
Table 12. Link between Master Clock Power Range and Frequencies
73
Table 13. Delays to Memory Access and Number of Wait States
73
Data Buffering
75
Figure 3. Structure of One Internal Buffer
75
Table 14. Internal Buffer Management
76
Figure 4. Timing to Fetch and Execute Instructions with Prefetch Disabled
77
Table 15. Configurations for Buffers and Speculative Reading
79
Figure 5. Timing to Fetch and Execute Instructions with Prefetch Enabled
79
Table 16. Dhrystone Performances in All Memory Interface Configurations
80
Writing/Erasing the NVM
81
Write/Erase Protocol
81
Unlocking/Locking Operations
82
Detailed Description of NVM Write/Erase Operations
85
Parallel Write Half-Page Flash Program Memory
91
Table 17. NVM Write/Erase Timings
94
Table 18. NVM Write/Erase Duration
94
Status Register
95
Memory Protection
96
RDP (Read out Protection)
97
Pcrop (Proprietary Code Read-Out Protection)
98
Table 19. Protection Level and Content of RDP Option Bytes
98
Figure 6. RDP Levels
98
Table 20. Link between Protection Bits of Flash_Wrprotx Register and Protected Address in Flash Program Memory
99
Protections against Unwanted Write/Erase Operations
100
Table 21. Memory Access Vs Mode, Protection and Flash Program Memory Sectors
100
Write/Erase Protection Management
101
Protection Errors
102
Write Protection Error Flag (WRPERR)
102
Read Error (RDERR)
102
NVM Interrupts
102
Hard Fault
103
Memory Interface Management
103
Operation Priority and Evolution
103
Read
103
Write/Erase
103
Table 22. Flash Interrupt Request
103
Option Byte Loading
104
Sequence of Operations
104
Read as Data While Write
104
Fetch While Write
104
Write While Another Write Operation Is Ongoing
105
Change the Number of Wait States While Reading
105
Power-Down
105
Flash Register Description
106
Read Registers
106
Write to Registers
106
Access Control Register (FLASH_ACR)
107
Program and Erase Control Register (FLASH_PECR)
108
Power-Down Key Register (FLASH_PDKEYR)
112
PECR Unlock Key Register (FLASH_PEKEYR)
112
Program and Erase Key Register (FLASH_PRGKEYR)
112
Option Bytes Unlock Key Register (FLASH_OPTKEYR)
113
Status Register (FLASH_SR)
114
Option Bytes Register (FLASH_OPTR)
116
Write Protection Register 1 (FLASH_WRPROT1)
118
Write Protection Register 2 (FLASH_WRPROT2)
119
Flash Register Map
120
Table 23. Flash Interface - Register Map and Reset Values
120
Option Bytes
121
Option Bytes Description
121
Table 24. Option Byte Format
121
Table 25. Option Byte Organization
121
Mismatch When Loading Protection Flags
122
Reloading Option Bytes by Software
122
Cyclic Redundancy Check Calculation Unit (CRC)
123
Introduction
123
CRC Main Features
123
CRC Functional Description
124
CRC Block Diagram
124
CRC Internal Signals
124
CRC Operation
124
Table 26. CRC Internal Input/Output Signals
124
Figure 7. CRC Calculation Unit Block Diagram
124
Polynomial Programmability
125
CRC Registers
126
CRC Data Register (CRC_DR)
126
CRC Independent Data Register (CRC_IDR)
126
CRC Control Register (CRC_CR)
127
CRC Initial Value (CRC_INIT)
128
CRC Polynomial (CRC_POL)
128
CRC Register Map
129
Table 27. CRC Register Map and Reset Values
129
Firewall (FW)
130
Introduction
130
Firewall Main Features
130
Firewall Functional Description
131
Firewall AMBA Bus Snoop
131
Functional Requirements
131
Debug Consideration
131
Figure 8. Stm32L0X3 Firewall Connection Schematics
131
Write Protection
132
Interrupts Management
132
Firewall Segments
132
Code Segment
132
Non-Volatile Data Segment
132
Volatile Data Segment
133
Segment Accesses and Properties
133
Segment Access Depending on the Firewall State
133
Table 28. Segment Accesses According to the Firewall State
133
Segments Properties
134
Firewall Initialization
134
Table 29. Segment Granularity and Area Ranges
134
Firewall States
135
Figure 9. Firewall Functional States
135
Opening the Firewall
136
Closing the Firewall
136
Firewall Registers
137
Code Segment Start Address (FW_CSSA)
137
Code Segment Length (FW_CSL)
137
Non-Volatile Data Segment Start Address (FW_NVDSSA)
138
Non-Volatile Data Segment Length (FW_NVDSL)
138
Volatile Data Segment Start Address (FW_VDSSA)
139
Volatile Data Segment Length (FW_VDSL)
139
Configuration Register (FW_CR)
140
Firewall Register Map
141
Table 30. Firewall Register Map and Reset Values
141
Power Control (PWR)
142
Power Supplies
142
Independent A/D and DAC Converter Supply and Reference Voltage
143
On Packages with V REF+ Pin
143
On Packages Without V REF+ Pin
143
Figure 10. Power Supply Overview
143
Independent LCD Supply
144
RTC and RTC Backup Registers
144
RTC Registers Access
144
Voltage Regulator
145
Dynamic Voltage Scaling Management
145
Range 1
145
Range 2 and 3
146
Table 31. Performance Versus VCORE Ranges
146
Figure 11. Performance Versus VDD and VCORE Range
146
Dynamic Voltage Scaling Configuration
147
Voltage Regulator and Clock Management When VDD Drops
147
Below 1.71 V
147
Voltage Regulator and Clock Management When Modifying the VCORE Range
147
Voltage Range and Limitations When VDD Ranges from 1.71 V to 2.0 V
148
Power Supply Supervisor
148
Figure 12. Power Supply Supervisors
149
Power-On Reset (Por)/Power-Down Reset (PDR)
150
Brown out Reset (BOR)
150
Figure 13. Power-On Reset/Power-Down Reset Waveform
150
Programmable Voltage Detector (PVD)
151
Figure 14. BOR Thresholds
151
Internal Voltage Reference (VREFINT)
152
Figure 15. PVD Thresholds
152
Low-Power Modes
153
Table 32. Summary of Low-Power Modes
153
Behavior of Clocks in Low-Power Modes
154
Sleep and Low-Power Sleep Modes
154
Stop and Standby Modes
154
Slowing down System Clocks
155
Peripheral Clock Gating
155
Low-Power Run Mode (LP Run)
155
Entering Low-Power Run Mode
155
Exiting Low-Power Run Mode
156
Entering Low-Power Mode
156
Exiting Low-Power Mode
156
Sleep Mode
157
I/O States in Sleep Mode
157
Entering Sleep Mode
157
Exiting Sleep Mode
157
Table 33. Sleep-Now
157
Low-Power Sleep Mode (LP Sleep)
158
I/O States in Low-Power Sleep Mode
158
Entering Low-Power Sleep Mode
158
Table 34. Sleep-On-Exit
158
Exiting Low-Power Sleep Mode
159
Table 35. Sleep-Now (Low-Power Sleep)
159
Stop Mode
160
I/O States in Low-Power Sleep Mode
160
Entering Stop Mode
160
Table 36. Sleep-On-Exit (Low-Power Sleep)
160
Exiting Stop Mode
161
Table 37. Stop Mode
162
Standby Mode
163
I/O States in Standby Mode
163
Entering Standby Mode
163
Exiting Standby Mode
163
Debug Mode
164
Waking up the Device from Stop and Standby Modes Using the RTC
164
And Comparators
164
Table 38. Standby Mode
164
RTC Auto-Wakeup (AWU) from the Stop Mode
165
RTC Auto-Wakeup (AWU) from the Standby Mode
165
Comparator Auto-Wakeup (AWU) from the Stop Mode
166
Power Control Registers
167
PWR Power Control Register (PWR_CR)
167
PWR Power Control/Status Register (PWR_CSR)
170
PWR Register Map
172
Table 39. PWR - Register Map and Reset Values
172
Reset and Clock Control (RCC)
173
Reset
173
System Reset
173
Software Reset
173
Low-Power Management Reset
173
Option Byte Loader Reset
173
Power Reset
174
RTC and Backup Registers Reset
174
Figure 16. Simplified Diagram of the Reset Circuit
174
Clocks
175
Figure 17. Clock Tree
177
HSE Clock
178
Table 40. HSE/LSE Clock Sources
178
External Source (HSE Bypass)
179
External Crystal/Ceramic Resonator (HSE Crystal)
179
HSI16 Clock
179
Calibration
179
MSI Clock
180
Calibration
180
HSI48 Clock
180
Pll
181
LSE Clock
182
External Source (LSE Bypass)
182
LSI Clock
182
LSI Measurement
182
System Clock (SYSCLK) Selection
183
System Clock Source Frequency Versus Voltage Range
183
HSE Clock Security System (CSS)
183
Table 41. System Clock Source Frequency
183
LSE Clock Security System
184
RTC and LCD Clock
184
Watchdog Clock
185
Clock-Out Capability
185
Internal/External Clock Measurement Using TIM21
185
Figure 18. Using TIM21 Channel 1 Input Capture to Measure
185
Frequencies
185
Clock-Independent System Clock Sources for TIM2/TIM21/TIM22
186
RCC Registers
187
Clock Control Register (RCC_CR)
187
Internal Clock Sources Calibration Register (RCC_ICSCR)
190
Clock Recovery RC Register (RCC_CRRCR)
191
Clock Configuration Register (RCC_CFGR)
192
Clock Interrupt Enable Register (RCC_CIER)
194
Clock Interrupt Flag Register (RCC_CIFR)
196
Clock Interrupt Clear Register (RCC_CICR)
197
GPIO Reset Register (RCC_IOPRSTR)
198
AHB Peripheral Reset Register (RCC_AHBRSTR)
199
APB2 Peripheral Reset Register (RCC_APB2RSTR)
200
APB1 Peripheral Reset Register (RCC_APB1RSTR)
201
GPIO Clock Enable Register (RCC_IOPENR)
204
AHB Peripheral Clock Enable Register (RCC_AHBENR)
205
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
207
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
209
GPIO Clock Enable in Sleep Mode Register (RCC_IOPSMENR)
212
AHB Peripheral Clock Enable in Sleep Mode Register (RCC_AHBSMENR)
213
APB2 Peripheral Clock Enable in Sleep Mode Register (RCC_APB2SMENR)
214
APB1 Peripheral Clock Enable in Sleep Mode Register (RCC_APB1SMENR)
215
Clock Configuration Register (RCC_CCIPR)
217
Control/Status Register (RCC_CSR)
219
RCC Register Map
223
Table 42. RCC Register Map and Reset Values
223
Clock Recovery System (CRS)
226
Introduction
226
CRS Main Features
226
CRS Implementation
226
Table 43. CRS Features
226
CRS Functional Description
227
CRS Block Diagram
227
Synchronization Input
227
Figure 19. CRS Block Diagram
227
Frequency Error Measurement
228
Figure 20. CRS Counter Behavior
228
Frequency Error Evaluation and Automatic Trimming
229
CRS Initialization and Configuration
229
RELOAD Value
229
FELIM Value
230
CRS Low-Power Modes
230
CRS Interrupts
230
Table 44. Effect of Low-Power Modes on CRS
230
Table 45. Interrupt Control Bits
230
CRS Registers
231
CRS Control Register (CRS_CR)
231
CRS Configuration Register (CRS_CFGR)
232
CRS Interrupt and Status Register (CRS_ISR)
233
CRS Interrupt Flag Clear Register (CRS_ICR)
235
CRS Register Map
236
Table 46. CRS Register Map and Reset Values
236
General-Purpose I/Os (GPIO)
237
Introduction
237
GPIO Main Features
237
GPIO Functional Description
237
Figure 21. Basic Structure of an I/O Port Bit
238
Figure 22. Basic Structure of a 5-Volt Tolerant I/O Port Bit
238
General-Purpose I/O (GPIO)
239
Table 47. Port Bit Configuration Table
239
I/O Pin Alternate Function Multiplexer and Mapping
240
I/O Port Control Registers
241
I/O Port Data Registers
241
I/O Data Bitwise Handling
241
GPIO Locking Mechanism
241
I/O Alternate Function Input/Output
242
External Interrupt/Wakeup Lines
242
Input Configuration
242
Output Configuration
243
Figure 23. Input Floating/Pull Up/Pull down Configurations
243
Alternate Function Configuration
244
Figure 24. Output Configuration
244
Analog Configuration
245
Figure 25. Alternate Function Configuration
245
Figure 26. High Impedance-Analog Configuration
245
Using the HSE or LSE Oscillator Pins as Gpios
246
Using the GPIO Pins in the RTC Supply Domain
246
GPIO Registers
246
GPIO Port Mode Register (Gpiox_Moder)
246
(X =A to E and H)
246
GPIO Port Output Type Register (Gpiox_Otyper)
247
(X = a to E and H)
247
GPIO Port Output Speed Register (Gpiox_Ospeedr)
247
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
248
(X = a to E and H)
248
GPIO Port Input Data Register (Gpiox_Idr)
248
GPIO Port Output Data Register (Gpiox_Odr)
249
(X = a to E and H)
249
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr)
249
GPIO Port Configuration Lock Register (Gpiox_Lckr)
249
GPIO Alternate Function Low Register (Gpiox_Afrl)
251
(X = a to E and H)
251
GPIO Alternate Function High Register (Gpiox_Afrh)
251
GPIO Port Bit Reset Register (Gpiox_Brr) (X = a to E and H)
252
GPIO Register Map
253
Table 48. GPIO Register Map and Reset Values
253
System Configuration Controller (SYSCFG)
255
Introduction
255
SYSCFG Registers
256
SYSCFG Memory Remap Register (SYSCFG_CFGR1)
256
SYSCFG Peripheral Mode Configuration Register (SYSCFG_CFGR2)
258
Reference Control and Status Register (SYSCFG_CFGR3)
259
SYSCFG External Interrupt Configuration Register 1
261
(Syscfg_Exticr1)
261
SYSCFG External Interrupt Configuration Register 2
262
(Syscfg_Exticr2)
262
(Syscfg_Exticr3)
262
SYSCFG External Interrupt Configuration Register 4
263
(Syscfg_Exticr4)
263
SYSCFG Register Map
263
Table 49. SYSCFG Register Map and Reset Values
263
Direct Memory Access Controller (DMA)
265
Introduction
265
DMA Main Features
265
DMA Implementation
266
Dma
266
DMA Request Mapping
266
DMA Controller
266
Table 50. DMA Implementation
266
Table 51. DMA Requests for each Channel
267
Figure 27. DMA Request Mapping
267
DMA Functional Description
268
DMA Block Diagram
268
DMA Transfers
269
Figure 28. DMA Block Diagram
269
DMA Arbitration
270
DMA Channels
271
Programmable Data Sizes
271
Pointer Incrementation
271
Channel Configuration Procedure
272
Channel State and Disabling a Channel
272
Circular Mode (in Memory-To-Peripheral/Peripheral-To-Memory Transfers)
273
Memory-To-Memory Mode
273
Peripheral-To-Peripheral Mode
274
Programming Transfer Direction, Assigning Source/Destination
274
DMA Data Width, Alignment and Endianness
274
Addressing AHB Peripherals Not Supporting Byte/Half-Word Write Transfers
275
Table 52. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)
275
DMA Error Management
276
DMA Interrupts
276
DMA Registers
276
Table 53. DMA Interrupt Requests
276
DMA Interrupt Status Register (DMA_ISR)
277
DMA Interrupt Flag Clear Register (DMA
279
DMA Channel X Configuration Register (Dma_Ccrx)
280
DMA Channel X Number of Data to Transfer Register (Dma_Cndtrx)
283
DMA Channel X Peripheral Address Register (Dma_Cparx)
284
DMA Channel X Memory Address Register (Dma_Cmarx)
284
DMA Channel Selection Register (DMA_CSELR)
286
DMA Register Map
286
Table 54. DMA Register Map and Reset Values
286
Nested Vectored Interrupt Controller (NVIC)
289
Main Features
289
Systick Calibration Value Register
289
Interrupt and Exception Vectors
289
Extended Interrupt and Event Controller (EXTI)
292
Introduction
292
EXTI Main Features
292
EXTI Functional Description
292
EXTI Block Diagram
293
Wakeup Event Management
293
Figure 29. Extended Interrupts and Events Controller (EXTI) Block Diagram
293
Peripherals Asynchronous Interrupts
294
Hardware Interrupt Selection
294
Hardware Event Selection
294
Software Interrupt/Event Selection
294
EXTI Interrupt/Event Line Mapping
295
Figure 30. Extended Interrupt/Event GPIO Mapping
295
Table 56. EXTI Lines Connections
296
EXTI Registers
297
EXTI Interrupt Mask Register (EXTI_IMR)
297
EXTI Event Mask Register (EXTI_EMR)
297
EXTI Rising Edge Trigger Selection Register (EXTI_RTSR)
298
Falling Edge Trigger Selection Register (EXTI_FTSR)
299
EXTI Software Interrupt Event Register (EXTI_SWIER)
299
EXTI Pending Register (EXTI_PR)
300
EXTI Register Map
301
Table 57. Extended Interrupt/Event Controller Register Map and Reset Values
301
Analog-To-Digital Converter (ADC)
302
Introduction
302
ADC Main Features
303
ADC Functional Description
304
ADC Pins and Internal Signals
304
Table 58. ADC Input/Output Pins
304
Figure 31. ADC Block Diagram
304
ADC Voltage Regulator (ADVREGEN)
305
Analog Reference for the ADC Internal Voltage Regulator
305
Table 59. ADC Internal Input/Output Signals
305
Table 60. External Triggers
305
ADVREG Enable Sequence
306
ADVREG Disable Sequence
306
Calibration (ADCAL)
306
Figure 32. ADC Calibration
307
Calibration Factor Forcing Software Procedure
308
ADC On-Off Control (ADEN, ADDIS, ADRDY)
308
Figure 33. Calibration Factor Forcing
308
ADC Clock (CKMODE, PRESC[3:0], LFMEN)
309
Figure 34. Enabling/Disabling the ADC
309
Figure 35. ADC Clock Scheme
309
Low Frequency
310
Table 61. Latency between Trigger and Start of Conversion
310
ADC Connectivity
311
Figure 36. ADC Connectivity
311
Configuring the ADC
312
Channel Selection (CHSEL, SCANDIR)
312
Temperature Sensor, VREFINT and LCD_VLCD1 Internal Channels
312
Programmable Sampling Time (SMP)
313
Single Conversion Mode (CONT = 0)
313
Continuous Conversion Mode (CONT = 1)
314
Starting Conversions (ADSTART)
314
Timings
315
Figure 37. Analog to Digital Conversion Time
315
Figure 38. ADC Conversion Timings
315
Stopping an Ongoing Conversion (ADSTP)
316
Conversion on External Trigger and Trigger Polarity (EXTSEL, EXTEN)
316
Table 62. Configuring the Trigger Polarity
316
Figure 39. Stopping an Ongoing Conversion
316
Discontinuous Mode (DISCEN)
317
Programmable Resolution (RES) - Fast Conversion Mode
317
End of Conversion, End of Sampling Phase (EOC, EOSMP Flags)
318
End of Conversion Sequence (EOS Flag)
318
Table 63. Tsar Timings Depending on Resolution
318
Example Timing Diagrams
319
Hardware/Software Triggers)
319
Figure 40. Single Conversions of a Sequence, Software Trigger
319
Figure 41. Continuous Conversion of a Sequence, Software Trigger
319
Figure 42. Single Conversions of a Sequence, Hardware Trigger
320
Figure 43. Continuous Conversions of a Sequence, Hardware Trigger
320
Data Management
321
Data Register and Data Alignment (ADC_DR, ALIGN)
321
ADC Overrun (OVR, OVRMOD)
321
Figure 44. Data Alignment and Resolution (Oversampling Disabled: OVSE = 0)
321
Managing a Sequence of Data Converted Without Using the DMA
322
Managing Converted Data Without Using the DMA Without Overrun
322
Managing Converted Data Using the DMA
322
Figure 45. Example of Overrun (OVR)
322
DMA One Shot Mode (DMACFG = 0)
323
DMA Circular Mode (DMACFG = 1)
323
Low-Power Features
324
Wait Mode Conversion
324
Figure 46. Wait Mode Conversion (Continuous Mode, Software Trigger)
324
Auto-Off Mode (AUTOFF)
325
Figure 47. Behavior with WAIT = 0, AUTOFF = 1
325
Analog Window Watchdog
326
Adc_Tr)
326
Description of the Analog Watchdog
326
ADC_AWD1_OUT Output Signal Generation
327
Table 64. Analog Watchdog Comparison
327
Table 65. Analog Watchdog Channel Selection
327
Figure 49. Analog Watchdog Guarded Area
327
Figure 50. ADC_AWD1_OUT Signal Generation
328
Analog Watchdog Threshold Control
329
Figure 51. ADC_AWD1_OUT Signal Generation (AWD Flag Not Cleared by Software)
329
Figure 52. ADC1_AWD_OUT Signal Generation (on a Single Channel)
329
Oversampler
330
Figure 53. Analog Watchdog Threshold Update
330
Table 66. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation
331
Figure 54. 20-Bit to 16-Bit Result Truncation
331
Figure 55. Numerical Example with 5-Bits Shift and Rounding
331
ADC Operating Modes Supported When Oversampling
332
Analog Watchdog
332
Triggered Mode
332
Temperature Sensor and Internal Reference Voltage
333
Figure 56. Triggered Oversampling Mode (TOVS Bit = 1)
333
Main Features
334
Reading the Temperature
334
Figure 57. Temperature Sensor and VREFINT Channel Block Diagram
334
Calculating the Actual V
335
Dda
335
Converting a Supply-Relative ADC Measurement to an Absolute Voltage Value
335
VLCD Voltage Monitoring
336
ADC Interrupts
336
Table 67. ADC Interrupts
336
ADC Registers
337
ADC Interrupt and Status Register (ADC_ISR)
337
ADC Interrupt Enable Register (ADC_IER)
338
ADC Control Register (ADC_CR)
340
ADC Configuration Register 1 (ADC_CFGR1)
342
ADC Configuration Register 2 (ADC_CFGR2)
346
ADC Sampling Time Register (ADC_SMPR)
347
ADC Watchdog Threshold Register (ADC_TR)
348
ADC Channel Selection Register (ADC_CHSELR)
348
ADC Data Register (ADC_DR)
349
ADC Calibration Factor (ADC_CALFACT)
349
ADC Common Configuration Register (ADC_CCR)
350
ADC Register Map
351
Table 68. ADC Register Map and Reset Values
351
Digital-To-Analog Converter (DAC)
353
Introduction
353
DAC1 Main Features
353
Table 69. DAC Pins
354
Figure 58. DAC Block Diagram
354
DAC Output Buffer Enable
355
DAC Channel Enable
355
Single Mode Functional Description
355
DAC Data Format
355
DAC Channel Conversion
355
Figure 59. Data Registers in Single DAC Channel Mode
355
Independent Trigger with Single LFSR Generation
356
Independent Trigger with Single Triangle Generation
356
Figure 60. Timing Diagram for Conversion with Trigger Disabled TEN = 0
356
DAC Output Voltage
357
DAC Trigger Selection
357
Table 70. External Triggers
357
Dual-Mode Functional Description
358
DAC Data Format
358
DAC Channel Conversion in Dual Mode
358
Description of Dual Conversion Modes
358
Figure 61. Data Registers in Dual DAC Channel Mode
358
Independent Trigger Without Wave Generation
359
Independent Trigger with Single LFSR Generation
359
Independent Trigger with Different LFSR Generation
359
Independent Trigger with Single Triangle Generation
360
Independent Trigger with Different Triangle Generation
360
Simultaneous Software Start
360
Simultaneous Trigger Without Wave Generation
360
Simultaneous Trigger with Single LFSR Generation
361
Simultaneous Trigger with Different LFSR Generation
361
Simultaneous Trigger with Single Triangle Generation
361
Simultaneous Trigger with Different Triangle Generation
362
DAC Output Voltage
362
DAC Trigger Selection
362
Noise Generation
362
Figure 62. DAC LFSR Register Calculation Algorithm
362
Triangle-Wave Generation
363
Figure 63. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
363
Figure 64. DAC Triangle Wave Generation
363
DMA Request
364
DMA Underrun
364
Figure 65. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
364
DAC Registers
365
DAC Control Register (DAC_CR)
365
DAC Software Trigger Register (DAC_SWTRIGR)
369
DAC Channel1 12-Bit Right-Aligned Data Holding Register
369
(Dac_Dhr12R1)
369
DAC Channel1 12-Bit Left-Aligned Data Holding Register
370
(Dac_Dhr12L1)
370
DAC Channel1 8-Bit Right-Aligned Data Holding Register
370
(Dac_Dhr8R1)
370
DAC Channel2 12-Bit Right-Aligned Data Holding Register
370
(Dac_Dhr12R2)
370
DAC Channel2 12-Bit Left-Aligned Data Holding Register
371
(Dac_Dhr12L2)
371
DAC Channel2 8-Bit Right-Aligned Data Holding Register
371
(Dac_Dhr8R2)
371
Dual DAC 12-Bit Right-Aligned Data Holding Register
372
(Dac_Dhr12Rd)
372
15.10.10 Dual DAC 12-Bit Left-Aligned Data Holding Register
372
(Dac_Dhr12Ld)
372
15.10.11 Dual DAC 8-Bit Right-Aligned Data Holding Register
372
(Dac_Dhr8Rd)
372
DAC Channel1 Data Output Register (DAC_DOR1)
373
DAC Channel2 Data Output Register (DAC_DOR2)
373
DAC Status Register (DAC_SR)
373
15.10.15 DAC Register Map
375
Table 71. DAC Register Map and Reset Values
375
Comparator (COMP)
377
Introduction
377
COMP Main Features
377
COMP Functional Description
378
COMP Block Diagram
378
COMP Pins and Internal Signals
378
Figure 66. Comparator 1 and 2 Block Diagrams
378
COMP Reset and Clocks
379
Comparator LOCK Mechanism
379
Power Mode
379
COMP Interrupts
379
COMP Registers
379
Comparator 1 Control and Status Register (COMP1_CSR)
379
Comparator 2 Control and Status Register (COMP2_CSR)
381
COMP Register Map
383
Table 72. COMP Register Map and Reset Values
383
Liquid Crystal Display Controller (LCD)
384
Introduction
384
Glossary
384
LCD Main Features
385
LCD Implementation
386
LCD Functional Description
386
General Description
386
Table 73. Implementation
386
Figure 67. LCD Controller Block Diagram
386
Frequency Generator
387
Table 74. Example of Frame Rate Calculation
387
Common Driver
388
COM Signal Bias
388
COM Signal Duty
389
Figure 68. 1/3 Bias, 1/4 Duty
389
Figure 69. Static Duty Case 1
390
Figure 70. Static Duty Case 2
390
To 1 Mux
391
Segment Driver
391
In the Case of 1/4 or 1/8 Duty
391
Figure 71. 1/2 Duty, 1/2 Bias
391
Figure 72. 1/3 Duty, 1/3 Bias
392
Figure 73. 1/4 Duty, 1/3 Bias
393
Figure 74. 1/8 Duty, 1/4 Bias
394
Blink
395
Voltage Generator and Contrast Control
395
LCD Supply Source
395
Table 75. Blink Frequency
395
LCD Intermediate Voltages
396
LCD Drive Selection
396
Figure 75. LCD Voltage Control
397
External Decoupling
398
Deadtime
398
Table 76. Vlcdrail Connections to GPIO Pins
398
Figure 76. Deadtime
398
Double Buffer Memory
399
COM and SEG Multiplexing
399
Output Pins Versus Duty Modes
399
Remapping Capability for Small Packages
399
Summary of COM and SEG Functions Versus Duty and Remap
400
Table 77. Remapping Capability
400
Figure 77. SEG/COM Mux Feature Example
403
Flowchart
404
Figure 78. Flowchart Example
404
LCD Low-Power Modes
405
LCD Interrupts
405
Start of Frame (SOF)
405
Update Display Done (UDD)
405
Table 78. LCD Behavior in Low-Power Modes
405
Table 79. LCD Interrupt Requests
405
LCD Registers
406
LCD Control Register (LCD_CR)
406
LCD Frame Control Register (LCD_FCR)
407
LCD Status Register (LCD_SR)
409
LCD Clear Register (LCD_CLR)
410
LCD Display Memory (LCD_RAM)
411
LCD Register Map
412
Table 80. LCD Register Map and Reset Values
412
Touch Sensing Controller (TSC)
414
Introduction
414
TSC Main Features
414
TSC Functional Description
415
TSC Block Diagram
415
Surface Charge Transfer Acquisition Overview
415
Figure 79. TSC Block Diagram
415
Figure 80. Surface Charge Transfer Analog I/O Group Structure
416
Reset and Clocks
417
Table 81. Acquisition Sequence Summary
417
Figure 81. Sampling Capacitor Voltage Variation
417
Charge Transfer Acquisition Sequence
418
Figure 82. Charge Transfer Acquisition Sequence
418
Spread Spectrum Feature
419
Max Count Error
419
Table 82. Spread Spectrum Deviation Versus AHB Clock Frequency
419
Figure 83. Spread Spectrum Variation Principle
419
Sampling Capacitor I/O and Channel I/O Mode Selection
420
Table 83. I/O State Depending on Its Mode and IODEF Bit Value
420
Acquisition Mode
421
I/O Hysteresis and Analog Switch Control
421
TSC Low-Power Modes
422
TSC Interrupts
422
Table 84. Effect of Low-Power Modes on TSC
422
Table 85. Interrupt Control Bits
422
TSC Registers
423
TSC Control Register (TSC_CR)
423
TSC Interrupt Enable Register (TSC_IER)
425
TSC Interrupt Clear Register (TSC_ICR)
426
TSC Interrupt Status Register (TSC_ISR)
427
TSC I/O Hysteresis Control Register (TSC_IOHCR)
427
TSC I/O Analog Switch Control Register (TSC_IOASCR)
428
TSC I/O Sampling Control Register (TSC_IOSCR)
428
TSC I/O Channel Control Register (TSC_IOCCR)
429
TSC I/O Group Control Status Register (TSC_IOGCSR)
429
TSC I/O Group X Counter Register (Tsc_Iogxcr)
430
TSC Register Map
431
Table 86. TSC Register Map and Reset Values
431
AES Hardware Accelerator (AES)
433
Introduction
433
AES Main Features
433
AES Implementation
434
AES Functional Description
434
AES Block Diagram
434
AES Internal Signals
434
Table 87. AES Internal Input/Output Signals
434
Figure 84. AES Block Diagram
434
AES Cryptographic Core
435
Overview
435
Typical Data Processing
435
Chaining Modes
435
Electronic Codebook (ECB) Mode
436
Figure 85. ECB Encryption and Decryption Principle
436
Cipher Block Chaining (CBC) Mode
437
Figure 86. CBC Encryption and Decryption Principle
437
Counter (CTR) Mode
438
AES Procedure to Perform a Cipher Operation
438
Introduction
438
Figure 87. CTR Encryption and Decryption Principle
438
Initialization of AES
439
Data Append
439
Figure 88. STM32 Cryptolib AES Flowchart Example
439
AES Decryption Key Preparation
441
AES Ciphertext Stealing and Data Padding
442
AES Task Suspend and Resume
442
Figure 89. Encryption Key Derivation for ECB/CBC Decryption (Mode 2)
442
AES Basic Chaining Modes (ECB, CBC)
443
Overview
443
Figure 90. Example of Suspend Mode Management
443
Figure 91. ECB Encryption
443
Figure 92. ECB Decryption
444
Figure 93. CBC Encryption
444
Figure 94. CBC Decryption
445
ECB/CBC Encryption Sequence
446
ECB/CBC Decryption Sequence
446
Figure 95. ECB/CBC Encryption (Mode 1)
446
Suspend/Resume Operations in ECB/CBC Modes
447
Figure 96. ECB/CBC Decryption (Mode 3)
447
Alternative Single ECB/CBC Decryption Using Mode 4
448
AES Counter (CTR) Mode
448
Overview
448
CTR Encryption and Decryption
449
Figure 97. Message Construction in CTR Mode
449
Figure 98. CTR Encryption
449
Table 88. CTR Mode Initialization Vector Definition
450
Figure 99. CTR Decryption
450
Suspend/Resume Operations in CTR Mode
451
AES Data Registers and Data Swapping
451
Data Input and Output
451
Data Swapping
451
Figure 100. 128-Bit Block Construction with Respect to Data Swap
452
Data Padding
453
AES Key Registers
453
AES Initialization Vector Registers
453
AES DMA Interface
453
Table 89. Key Endianness in Aes_Keyrx Registers
453
Data Input Using DMA
454
Data Output Using DMA
454
Table 90. DMA Channel Configuration for Memory-To-AES Data Transfer
454
Figure 101. DMA Transfer of a 128-Bit Data Block During Input Phase
454
DMA Operation in Different Operating Modes
455
Table 91. DMA Channel Configuration for AES-To-Memory Data Transfer
455
Figure 102. DMA Transfer of a 128-Bit Data Block During Output Phase
455
AES Error Management
456
Read Error Flag (RDERR)
456
Write Error Flag (WDERR)
456
AES Interrupts
456
AES Processing Latency
457
Table 92. AES Interrupt Requests
457
Table 93. Processing Latency (in Clock Cycle)
457
Figure 103. AES Interrupt Signal Generation
457
AES Registers
458
AES Control Register (AES_CR)
458
AES Status Register (AES_SR)
460
AES Data Input Register (AES_DINR)
461
AES Data Output Register (AES_DOUTR)
461
AES Key Register 0 (AES_KEYR0)
462
AES Key Register 1 (AES_KEYR1)
463
AES Key Register 2 (AES_KEYR2)
463
AES Key Register 3 (AES_KEYR3)
463
AES Initialization Vector Register 0 (AES_IVR0)
464
AES Initialization Vector Register 1 (AES_IVR1)
464
AES Initialization Vector Register 2 (AES_IVR2)
465
AES Initialization Vector Register 3 (AES_IVR3)
465
AES Register Map
465
Table 94. AES Register Map and Reset Values
465
True Random Number Generator (RNG)
467
Introduction
467
RNG Main Features
467
RNG Functional Description
468
RNG Block Diagram
468
RNG Internal Signals
468
Table 95. RNG Internal Input/Output Signals
468
Figure 104. RNG Block Diagram
468
Random Number Generation
469
Figure 105. Entropy Source Model
469
Noise Source
470
Post Processing
470
Output Buffer
470
Health Checks
471
RNG Initialization
471
RNG Operation
471
Normal Operations
471
Low-Power Operations
472
Software Post-Processing
472
RNG Clocking
472
Error Management
472
Clock Error Detection
472
Noise Source Error Detection
473
RNG Low-Power Usage
473
RNG Interrupts
473
RNG Processing Time
473
Table 96. RNG Interrupt Requests
473
RNG Entropy Source Validation
474
Introduction
474
Validation Conditions
474
Data Collection
474
RNG Registers
475
RNG Control Register (RNG_CR)
475
RNG Status Register (RNG_SR)
476
RNG Data Register (RNG_DR)
477
RNG Register Map
478
Table 97. RNG Register Map and Reset Map
478
General-Purpose Timers (TIM2/TIM3)
479
TIM2/TIM3 Introduction
479
TIM2/TIM3 Main Features
479
Figure 106. General-Purpose Timer Block Diagram
480
TIM2/TIM3 Functional Description
481
Time-Base Unit
481
Prescaler Description
481
Figure 107. Counter Timing Diagram with Prescaler Division Change from 1 to 2
482
Figure 108. Counter Timing Diagram with Prescaler Division Change from 1 to 4
482
Counter Modes
483
Upcounting Mode
483
Figure 109. Counter Timing Diagram, Internal Clock Divided by 1
483
Figure 110. Counter Timing Diagram, Internal Clock Divided by 2
484
Figure 111. Counter Timing Diagram, Internal Clock Divided by 4
484
Figure 112. Counter Timing Diagram, Internal Clock Divided by N
485
Figure 113. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
485
Downcounting Mode
486
Figure 114. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
486
Figure 115. Counter Timing Diagram, Internal Clock Divided by 1
487
Figure 116. Counter Timing Diagram, Internal Clock Divided by 2
487
Figure 117. Counter Timing Diagram, Internal Clock Divided by 4
488
Figure 118. Counter Timing Diagram, Internal Clock Divided by N
488
Center-Aligned Mode (Up/Down Counting)
489
Figure 119. Counter Timing Diagram, Update Event When Repetition Counter
489
Is Not Used
489
Figure 120. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
490
Figure 121. Counter Timing Diagram, Internal Clock Divided by 2
491
Figure 122. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
491
Figure 123. Counter Timing Diagram, Internal Clock Divided by N
492
Figure 124. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
492
Clock Selection
493
Internal Clock Source (CK_INT)
493
Figure 125. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
493
External Clock Source Mode 1
494
Figure 126. Control Circuit in Normal Mode, Internal Clock Divided by 1
494
Figure 127. TI2 External Clock Connection Example
494
Figure 128. Control Circuit in External Clock Mode 1
495
External Clock Source Mode 2
496
Figure 129. External Trigger Input Block
496
Capture/Compare Channels
497
Figure 130. Control Circuit in External Clock Mode 2
497
Figure 131. Capture/Compare Channel (Example: Channel 1 Input Stage)
498
Figure 132. Capture/Compare Channel 1 Main Circuit
498
Input Capture Mode
499
Figure 133. Output Stage of Capture/Compare Channel (Channel 1)
499
PWM Input Mode
501
Figure 134. PWM Input Mode Timing
501
Forced Output Mode
502
Output Compare Mode
502
PWM Mode
503
Figure 135. Output Compare Mode, Toggle on OC1
503
PWM Edge-Aligned Mode
504
Figure 136. Edge-Aligned PWM Waveforms (ARR=8)
504
Downcounting Configuration
505
PWM Center-Aligned Mode
505
Figure 137. Center-Aligned PWM Waveforms (ARR=8)
506
One-Pulse Mode
507
Figure 138. Example of One-Pulse Mode
507
Particular Case: Ocx Fast Enable
508
Clearing the Ocxref Signal on an External Event
508
Encoder Interface Mode
509
Figure 139. Clearing Timx Ocxref
509
Table 98. Counting Direction Versus Encoder Signals
510
Timer Input XOR Function
511
Figure 140. Example of Counter Operation in Encoder Interface Mode
511
Figure 141. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
511
Timers and External Trigger Synchronization
512
Slave Mode: Reset Mode
512
Figure 142. Control Circuit in Reset Mode
512
Slave Mode: Gated Mode
513
Figure 143. Control Circuit in Gated Mode
513
Slave Mode: Trigger Mode
514
Figure 144. Control Circuit in Trigger Mode
514
Slave Mode: External Clock Mode 2 + Trigger Mode
515
Timer Synchronization
516
Using One Timer as Prescaler for Another Timer
516
Figure 145. Control Circuit in External Clock Mode 2 + Trigger Mode
516
Figure 146. Master/Slave Timer Example
516
Using One Timer to Enable Another Timer
517
Figure 147. Gating Timer y with OC1REF of Timer X
518
Using One Timer to Start Another Timer
519
Figure 148. Gating Timer y with Enable of Timer X
519
Figure 149. Triggering Timer y with Update of Timer X
520
Figure 150. Triggering Timer y with Enable of Timer X
520
Starting 2 Timers Synchronously in Response to an External Trigger
521
Figure 151. Triggering Timer X and y with Timer X TI1 Input
521
Debug Mode
522
TIM2/TIM3 Registers
523
Timx Control Register 1 (Timx_Cr1)
523
Timx Control Register 2 (Timx_Cr2)
525
Timx Slave Mode Control Register (Timx_Smcr)
526
Table 99. TIM2/TIM3 Internal Trigger Connection
527
Timx Dma/Interrupt Enable Register (Timx_Dier)
528
Timx Status Register (Timx_Sr)
529
Timx Event Generation Register (Timx_Egr)
531
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
532
Output Compare Mode
532
Input Capture Mode
533
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
535
Output Compare Mode
535
Input Capture Mode
536
Timx Capture/Compare Enable Register (Timx_Ccer)
536
Table 100. Output Control Bit for Standard Ocx Channels
537
Timx Counter (Timx_Cnt)
538
Timx Prescaler (Timx_Psc)
538
Timx Auto-Reload Register (Timx_Arr)
538
Timx Capture/Compare Register 1 (Timx_Ccr1)
539
Timx Capture/Compare Register 2 (Timx_Ccr2)
539
Timx Capture/Compare Register 3 (Timx_Ccr3)
540
Timx Capture/Compare Register 4 (Timx_Ccr4)
540
Timx DMA Control Register (Timx_Dcr)
541
Timx DMA Address for Full Transfer (Timx_Dmar)
541
Example of How to Use the DMA Burst Feature
542
TIM2 Option Register (TIM2_OR)
543
TIM3 Option Register (TIM3_OR)
544
Timx Register Map
545
Table 101. TIM2/3 Register Map and Reset Values
545
General-Purpose Timers (TIM21/22)
547
Introduction
547
TIM21/22 Main Features
547
Figure 152. General-Purpose Timer Block Diagram (TIM21/22)
548
TIM21/22 Functional Description
549
Timebase Unit
549
Prescaler Description
549
Figure 153. Counter Timing Diagram with Prescaler Division Change from 1 to 2
550
Counter Modes
551
Upcounting Mode
551
Figure 154. Counter Timing Diagram with Prescaler Division Change from 1 to 4
551
Figure 155. Counter Timing Diagram, Internal Clock Divided by 1
552
Figure 156. Counter Timing Diagram, Internal Clock Divided by 2
553
Figure 157. Counter Timing Diagram, Internal Clock Divided by 4
553
Figure 158. Counter Timing Diagram, Internal Clock Divided by N
554
Preloaded)
554
Downcounting Mode
555
Preloaded)
555
Figure 161. Counter Timing Diagram, Internal Clock Divided by 1
556
Figure 162. Counter Timing Diagram, Internal Clock Divided by 2
556
Figure 163. Counter Timing Diagram, Internal Clock Divided by 4
557
Figure 164. Counter Timing Diagram, Internal Clock Divided by N
557
Center-Aligned Mode (Up/Down Counting)
558
Figure 165. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
559
Figure 166. Counter Timing Diagram, Internal Clock Divided by 2
559
Figure 167. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
560
Figure 168. Counter Timing Diagram, Internal Clock Divided by N
560
Figure 169. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
561
Figure 170. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
561
Clock Selection
562
Internal Clock Source (CK_INT)
562
Figure 171. Control Circuit in Normal Mode, Internal Clock Divided by 1
562
Figure 172. TI2 External Clock Connection Example
563
External Clock Source Mode 2
564
Figure 173. Control Circuit in External Clock Mode 1
564
Figure 174. External Trigger Input Block
564
Capture/Compare Channels
565
Figure 175. Control Circuit in External Clock Mode 2
565
Figure 176. Capture/Compare Channel (Example: Channel 1 Input Stage)
566
Figure 177. Capture/Compare Channel 1 Main Circuit
566
Input Capture Mode
567
Figure 178. Output Stage of Capture/Compare Channel (Channel 1 and 2)
567
PWM Input Mode
569
Figure 179. PWM Input Mode Timing
569
Forced Output Mode
570
Output Compare Mode
570
PWM Mode
571
Figure 180. Output Compare Mode, Toggle on OC1
571
Figure 181. Edge-Aligned PWM Waveforms (ARR=8)
572
PWM Center-Aligned Mode
573
Figure 182. Center-Aligned PWM Waveforms (ARR=8)
573
Hints on Using Center-Aligned Mode
574
Clearing the Ocxref Signal on an External Event
574
One-Pulse Mode
575
Figure 183. Clearing Timx Ocxref
575
Figure 184. Example of One Pulse Mode
576
Particular Case: Ocx Fast Enable
577
Encoder Interface Mode
577
Table 102. Counting Direction Versus Encoder Signals
578
Figure 185. Example of Counter Operation in Encoder Interface Mode
578
TIM21/22 External Trigger Synchronization
579
Slave Mode: Reset Mode
579
Figure 186. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
579
Slave Mode: Gated Mode
580
Figure 187. Control Circuit in Reset Mode
580
Slave Mode: Trigger Mode
581
Figure 188. Control Circuit in Gated Mode
581
Timer Synchronization (TIM21/22)
582
Debug Mode
582
Figure 189. Control Circuit in Trigger Mode
582
TIM21/22 Registers
583
TIM21/22 Control Register 1 (Timx_Cr1)
583
TIM21/22 Control Register 2 (Timx_Cr2)
585
TIM21/22 Slave Mode Control Register (Timx_Smcr)
586
Table 103. Timx Internal Trigger Connection
588
TIM21/22 Interrupt Enable Register (Timx_Dier)
589
TIM21/22 Status Register (Timx_Sr)
589
TIM21/22 Event Generation Register (Timx_Egr)
591
TIM21/22 Capture/Compare Mode Register 1 (Timx_Ccmr1)
592
Output Compare Mode
592
Input Capture Mode
594
TIM21/22 Capture/Compare Enable Register (Timx_Ccer)
595
TIM21/22 Counter (Timx_Cnt)
596
TIM21/22 Prescaler (Timx_Psc)
596
TIM21/22 Auto-Reload Register (Timx_Arr)
596
Table 104. Output Control Bit for Standard Ocx Channels
596
TIM21/22 Capture/Compare Register 1 (Timx_Ccr1)
597
TIM21/22 Capture/Compare Register 2 (Timx_Ccr2)
597
TIM21 Option Register (TIM21_OR)
598
TIM22 Option Register (TIM22_OR)
599
TIM21/22 Register Map
600
Table 105. TIM21/22 Register Map and Reset Values
600
Basic Timers (TIM6/7)
602
Introduction
602
TIM6/7 Main Features
602
Figure 190. Basic Timer Block Diagram
602
TIM6/7 Functional Description
603
Time-Base Unit
603
Prescaler Description
603
Figure 191. Counter Timing Diagram with Prescaler Division Change from 1 to 2
604
Figure 192. Counter Timing Diagram with Prescaler Division Change from 1 to 4
604
Counting Mode
605
Figure 193. Counter Timing Diagram, Internal Clock Divided by 1
605
Figure 194. Counter Timing Diagram, Internal Clock Divided by 2
606
Figure 195. Counter Timing Diagram, Internal Clock Divided by 4
606
Figure 196. Counter Timing Diagram, Internal Clock Divided by N
607
Preloaded)
607
Clock Source
608
Preloaded)
608
Debug Mode
609
Figure 199. Control Circuit in Normal Mode, Internal Clock Divided by 1
609
TIM6/7 Registers
610
TIM6/7 Control Register 1 (Timx_Cr1)
610
TIM6/7 Control Register 2 (Timx_Cr2)
611
TIM6/7 Dma/Interrupt Enable Register (Timx_Dier)
611
TIM6/7 Status Register (Timx_Sr)
612
TIM6/7 Event Generation Register (Timx_Egr)
612
TIM6/7 Counter (Timx_Cnt)
612
TIM6/7 Prescaler (Timx_Psc)
613
TIM6/7 Auto-Reload Register (Timx_Arr)
613
TIM6/7 Register Map
614
Table 106. TIM6/7 Register Map and Reset Values
614
Low-Power Timer (LPTIM)
615
Introduction
615
LPTIM Main Features
615
LPTIM Implementation
616
LPTIM Functional Description
616
LPTIM Block Diagram
616
Table 107. Stm32L0X3 LPTIM Features
616
Figure 200. Low-Power Timer Block Diagram
616
LPTIM Trigger Mapping
617
LPTIM Reset and Clocks
617
Glitch Filter
617
Table 108. LPTIM1 External Trigger Connection
617
Prescaler
618
Table 109. Prescaler Division Ratios
618
Figure 201. Glitch Filter Timing Diagram
618
Trigger Multiplexer
619
Operating Mode
619
One-Shot Mode
619
Continous Mode
620
Figure 202. LPTIM Output Waveform, Single Counting Mode Configuration
620
Figure 203. LPTIM Output Waveform, Single Counting Mode Configuration
620
And Set-Once Mode Activated (WAVE Bit Is Set)
620
Timeout Function
621
Waveform Generation
621
Figure 204. LPTIM Output Waveform, Continuous Counting Mode Configuration
621
Register Update
622
Figure 205. Waveform Generation
622
Counter Mode
623
Timer Enable
624
Encoder Mode
624
Table 110. Encoder Counting Scenarios
624
Debug Mode
625
LPTIM Low-Power Modes
625
Table 111. Effect of Low-Power Modes on the LPTIM
625
Figure 206. Encoder Mode Counting Sequence
625
LPTIM Interrupts
626
LPTIM Registers
626
Table 112. Interrupt Events
626
LPTIM Interrupt and Status Register (LPTIM_ISR)
627
LPTIM Interrupt Clear Register (LPTIM_ICR)
628
LPTIM Interrupt Enable Register (LPTIM_IER)
628
LPTIM Configuration Register (LPTIM_CFGR)
629
LPTIM Control Register (LPTIM_CR)
632
LPTIM Compare Register (LPTIM_CMP)
633
LPTIM Autoreload Register (LPTIM_ARR)
634
LPTIM Counter Register (LPTIM_CNT)
634
LPTIM Register Map
635
Table 113. LPTIM Register Map and Reset Values
635
Independent Watchdog (IWDG)
636
Introduction
636
IWDG Main Features
636
IWDG Functional Description
636
IWDG Block Diagram
636
Figure 207. Independent Watchdog Block Diagram
636
Window Option
637
Configuring the IWDG When the Window Option Is Enabled
637
Configuring the IWDG When the Window Option Is Disabled
637
Hardware Watchdog
638
Register Access Protection
638
Debug Mode
638
IWDG Registers
639
IWDG Key Register (IWDG_KR)
639
IWDG Prescaler Register (IWDG_PR)
640
IWDG Reload Register (IWDG_RLR)
641
IWDG Status Register (IWDG_SR)
642
IWDG Window Register (IWDG_WINR)
643
IWDG Register Map
644
Table 114. IWDG Register Map and Reset Values
644
System Window Watchdog (WWDG)
645
Introduction
645
WWDG Main Features
645
WWDG Functional Description
645
WWDG Block Diagram
646
Enabling the Watchdog
646
Controlling the Down-Counter
646
How to Program the Watchdog Timeout
646
Figure 208. Watchdog Block Diagram
646
Figure 209. Window Watchdog Timing Diagram
647
Debug Mode
648
WWDG Interrupts
648
WWDG Registers
648
WWDG Control Register (WWDG_CR)
648
WWDG Configuration Register (WWDG_CFR)
649
WWDG Status Register (WWDG_SR)
649
WWDG Register Map
650
Table 115. WWDG Register Map and Reset Values
650
Real-Time Clock (RTC)
651
Introduction
651
RTC Main Features
652
RTC Implementation
652
Table 116. RTC Implementation
652
RTC Functional Description
653
RTC Block Diagram
653
Figure 210. RTC Block Diagram
653
Table 117. RTC Pin PC13 Configuration
654
Table 118. RTC_OUT Mapping
655
Table 119. Effect of Low-Power Modes on RTC
668
Table 120. Interrupt Control Bits
668
RTC Control Register (RTC_CR)
671
RTC Initialization and Status Register (RTC_ISR)
674
RTC Prescaler Register (RTC_PRER)
677
RTC Wakeup Timer Register (RTC_WUTR)
678
RTC Alarm a Register (RTC_ALRMAR)
679
RTC Alarm B Register (RTC_ALRMBR)
680
RTC Write Protection Register (RTC_WPR)
681
RTC Sub Second Register (RTC_SSR)
681
RTC Shift Control Register (RTC_SHIFTR)
682
RTC Timestamp Time Register (RTC_TSTR)
683
RTC Timestamp Date Register (RTC_TSDR)
684
RTC Time-Stamp Sub Second Register (RTC_TSSSR)
685
RTC Calibration Register (RTC_CALR)
686
RTC Tamper Configuration Register (RTC_TAMPCR)
687
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
690
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
691
RTC Option Register (RTC_OR)
692
RTC Backup Registers (Rtc_Bkpxr)
692
RTC Register Map
693
Table 121. RTC Register Map and Reset Values
693
Inter-Integrated Circuit (I2C) Interface
695
Introduction
695
I2C Main Features
695
I2C Implementation
696
I2C Functional Description
696
Table 122. Stm32L0X3 I2C Features
696
I2C1/3 Block Diagram
697
Figure 211. I2C1/3 Block Diagram
697
I2C2 Block Diagram
698
Figure 212. I2C2 Block Diagram
698
I2C Pins and Internal Signals
699
I2C Clock Requirements
699
Mode Selection
699
Table 123. I2C Input/Output Pins
699
Table 124. I2C Internal Input/Output Signals
699
Communication Flow
700
I2C Initialization
700
Enabling and Disabling the Peripheral
700
Noise Filters
700
Figure 213. I2C Bus Protocol
700
Table 125. Comparison of Analog Vs. Digital Filters
701
I2C Timings
702
Figure 214. Setup and Hold Timings
702
Software Reset
705
Figure 215. I2C Initialization Flowchart
705
Data Transfer
706
Figure 216. Data Reception
706
Figure 217. Data Transmission
707
Table 127. I2C Configuration
708
Figure 218. Slave Initialization Flowchart
710
Figure 219. Transfer Sequence Flowchart for I2C Slave Transmitter
712
Nostretch= 0
712
Figure 220. Transfer Sequence Flowchart for I2C Slave Transmitter
713
Nostretch= 1
713
Figure 221. Transfer Bus Diagrams for I2C Slave Transmitter
714
Figure 222. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
715
Figure 223. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
716
Figure 224. Transfer Bus Diagrams for I2C Slave Receiver
716
Figure 225. Master Clock Generation
718
Table 128. I2C-Smbus Specification Clock Timings
719
Figure 226. Master Initialization Flowchart
720
Figure 227. 10-Bit Address Read Access with HEAD10R=0
720
Figure 228. 10-Bit Address Read Access with HEAD10R=1
721
Figure 229. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes
722
Figure 230. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes
723
Figure 231. Transfer Bus Diagrams for I2C Master Transmitter
724
Figure 232. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes
726
Figure 233. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes
727
Figure 234. Transfer Bus Diagrams for I2C Master Receiver
728
Table 129. Examples of Timing Settings for Fi2Cclk = 8 Mhz
729
Table 130. Examples of Timings Settings for Fi2Cclk = 16 Mhz
729
Table 131. Smbus Timeout Specifications
731
Figure 235. Timeout Intervals for T
732
LOW:SEXT , T LOW:MEXT
732
Table 132. Smbus with PEC Configuration
734
Table 133. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies
735
(Max T IDLE = 50 Μs)
735
Figure 236. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
736
Figure 237. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
737
Figure 238. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
738
Figure 239. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
739
Figure 240. Bus Transfer Diagrams for Smbus Master Transmitter
740
Figure 241. Bus Transfer Diagrams for Smbus Master Receiver
742
Table 136. Effect of Low-Power Modes on the I2C
746
Table 137. I2C Interrupt Requests
747
Table 138. I2C Register Map and Reset Values
762
Table 139. Stm32L0X3 USART/LPUART Features
766
Figure 242. USART Block Diagram
768
Figure 243. Word Length Programming
770
Figure 244. Configurable Stop Bits
772
Figure 245. TC/TXE Behavior When Transmitting
773
Figure 246. Start Bit Detection When Oversampling by 16 or 8
774
Figure 247. Data Sampling When Oversampling by 16
777
Table 140. Noise Detection from Sampled Data
778
Figure 248. Data Sampling When Oversampling by 8
778
Table 141. Error Calculation for Programmed Baud Rates at F
781
Oversampling by 16 or by 8
781
Table 142. Tolerance of the USART Receiver When BRR [3:0] = 0000
782
Table 143. Tolerance of the USART Receiver When BRR [3:0] Is Different from 0000
782
Figure 249. Mute Mode Using Idle Line Detection
785
Figure 250. Mute Mode Using Address Mark Detection
786
Table 144. Frame Formats
787
Figure 251. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
789
Figure 252. Break Detection in LIN Mode Vs. Framing Error Detection
790
Figure 253. USART Example of Synchronous Transmission
791
Figure 254. USART Data Clock Timing Diagram (M Bits = 00)
791
Figure 255. USART Data Clock Timing Diagram (M Bits = 01)
792
Figure 256. RX Data Setup/Hold Time
792
Figure 257. ISO 7816-3 Asynchronous Protocol
794
Figure 258. Parity Error Detection Using the 1.5 Stop Bits
795
Figure 259. Irda SIR ENDEC- Block Diagram
799
Figure 260. Irda Data Modulation (3/16) -Normal Mode
800
Figure 261. Transmission Using DMA
801
Figure 262. Reception Using DMA
802
Figure 263. Hardware Flow Control between 2 Usarts
802
Figure 264. RS232 RTS Flow Control
803
Figure 265. RS232 CTS Flow Control
804
Table 145. Effect of Low-Power Modes on the USART
806
Table 146. USART Interrupt Requests
806
Figure 266. USART Interrupt Mapping Diagram
807
Table 147. USART Register Map and Reset Values
829
Table 148. Stm32L0X3 USART/LPUART Features
833
Figure 267. LPUART Block Diagram
834
Figure 268. Word Length Programming
836
Figure 269. Configurable Stop Bits
837
Figure 270. TC/TXE Behavior When Transmitting
839
Table 149. Error Calculation for Programmed Baud Rates at Fck = 32.768 Khz
843
Table 150. Error Calculation for Programmed Baud Rates at Fck = 32 Mhz
843
Table 151. Tolerance of the LPUART Receiver
844
Figure 271. Mute Mode Using Idle Line Detection
846
Table 152. Frame Formats
847
Figure 272. Mute Mode Using Address Mark Detection
847
Figure 273. Transmission Using DMA
850
Figure 274. Reception Using DMA
851
Figure 275. Hardware Flow Control between 2 Lpuarts
851
Figure 276. RS232 RTS Flow Control
852
Figure 277. RS232 CTS Flow Control
853
Table 153. Effect of Low-Power Modes on the LPUART
856
Table 154. LPUART Interrupt Requests
856
Figure 278. LPUART Interrupt Mapping Diagram
857
Table 155. LPUART Register Map and Reset Values
872
Table 156. Stm32L0X3 SPI Implementation
874
Figure 279. SPI Block Diagram
875
Figure 280. Full-Duplex Single Master/ Single Slave Application
876
Figure 281. Half-Duplex Single Master/ Single Slave Application
877
Figure 282. Simplex Single Master/Single Slave Application
878
Slave in Receive-Only Mode)
878
Figure 283. Master and Three Independent Slaves
879
Figure 284. Multi-Master Application
880
Figure 285. Hardware/Software Slave Select Management
881
Figure 286. Data Clock Timing Diagram
883
Figure 287. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
886
Figure 288. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
887
Figure 289. Transmission Using DMA
889
Figure 290. Reception Using DMA
890
Figure 291. TI Mode Transfer
893
Table 157. SPI Interrupt Requests
895
Figure 292. I
896
Figure 293. Full-Duplex Communication
898
Figure 294. I S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
899
Figure 295. I S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
899
Figure 296. Transmitting 0X8Eaa33
900
Figure 297. Receiving 0X8Eaa33
900
Figure 298. I
900
Figure 299. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
901
Figure 300. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
901
Figure 301. MSB Justified 24-Bit Frame Length with CPOL = 0
901
Figure 302. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
902
Figure 303. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
902
Figure 304. LSB Justified 24-Bit Frame Length with CPOL = 0
902
Figure 305. Operations Required to Transmit 0X3478Ae
903
Figure 306. Operations Required to Receive 0X3478Ae
903
Figure 307. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
903
Figure 308. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
904
Figure 309. PCM Standard Waveforms (16-Bit)
904
Figure 310. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
904
Figure 311. Audio Sampling Frequency Definition
905
Figure 312. I
905
Table 158. Audio-Frequency Precision Using Standard 8 Mhz HSE
906
Table 159. I
912
Table 160. SPI Register Map and Reset Values
922
Table 161. Stm32L0X3 USB Implementation
923
Figure 313. USB Peripheral Block Diagram
924
Figure 314. Packet Buffer Areas with Examples of Buffer Description Table Locations
928
Table 162. Double-Buffering Buffer Flag Definition
933
Table 163. Bulk Double-Buffering Memory Buffers Usage
933
Table 164. Isochronous Memory Buffers Usage
935
Table 165. Resume Event Detection
936
Table 166. Reception Status Encoding
949
Table 167. Endpoint Type Encoding
949
Table 168. Endpoint Kind Meaning
949
Table 169. Transmission Status Encoding
950
Table 170. Definition of Allocated Buffer Memory
953
Table 171. USB Register Map and Reset Values
954
Figure 315. Block Diagram of Stm32L0X3 MCU and Cortex
956
Table 172. SW Debug Port Pins
957
Table 174. Packet Request (8-Bits)
959
Table 175. ACK Response (3 Bits)
960
Table 176. DATA Transfer (33 Bits)
960
Table 177. SW-DP Registers
961
Table 178. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
962
Table 179. Core Debug Registers
963
Table 180. DBG Register Map and Reset Values
970
Table 181. Document Revision History
1021
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ST STM32L0x3 Specifications
General
Brand
ST
Model
STM32L0x3
Category
Microcontrollers
Language
English
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