Reset and clock control (RCC) RM0367
178/1043 RM0367 Rev 7
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
f
CLK
acts as Cortex
®
-M0+ free running clock. For more details refer to the Section 33:
Debug support (DBG).
7.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Table 40. HSE/LSE clock sources
Clock source Hardware configuration
External clock for
category 3 and 5
devices
External clock
MSv31915V1
OSC_IN OSC_OUT
GPIO
External
source
External
source
CK_IN
GPIO
MSv36151V1
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