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RM0367 Rev 7 555/1043

RM0367 General-purpose timers (TIM21/22)

601

Figure 160. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded)

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a

counter underflow event.

An Update event can be generate at each counter underflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller)

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1

preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter restarts from the current auto-reload value, whereas the counter of the

prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when

clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is

reloaded, so that the next period is the expected one.

MS31083V2

CK_PSC

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter overflow

Update interrupt flag

(UIF)

03 04 05

07F1

F3 F4

F5F0

CEN

Auto-reload preload

Write a new value in TIMx_ARR

Auto-reload shadow

ST STM32L0x3 User Manual

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