RM0367 Rev 7 433/1043
RM0367 AES hardware accelerator (AES)
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19 AES hardware accelerator (AES)
19.1 Introduction
The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and
implementation fully compliant with the advanced encryption standard (AES) defined in
Federal information processing standards (FIPS) publication 197.
Multiple chaining modes are supported (ECB, CBC, CTR), for key size of 128 bits.
The AES accelerator is a 32-bit AHB peripheral. It supports DMA single transfers for
incoming and outgoing data (two DMA channels required).
The AES peripheral provides hardware acceleration to AES cryptographic algorithms
packaged in STM32 cryptographic library.
AES is an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated and write accesses are ignored).
19.2 AES main features
• Compliance with NIST “Advanced encryption standard (AES), FIPS publication 197”
from November 2001
• 128-bit data block processing
• Support for cipher key length of 128-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
• 213 clock cycle latency for processing one 128-bit block of data
• Integrated key scheduler with its key derivation stage (ECB or CBC decryption only)
• AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
• 128-bit register for storing the cryptographic key (four 32-bit registers)
• 128-bit register for storing initialization vector (four 32-bit registers)
– Used for the initialization vector when AES is configured in CBC mode or for the
32-bit counter initialization when CTR mode is selected
• 32-bit buffer for data input and output
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data-swapping logic to support 1-, 8-, 16- or 32-bit data
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