Liquid crystal display controller (LCD) RM0367
396/1043 RM0367 Rev 7
LCD intermediate voltages
The LCD intermediate voltage levels are generated through an internal resistor divider
network as shown in Figure 75.
The LCD voltage generator issues intermediate voltage levels between V
SS
and V
LCD
:
• 1/3 V
LCD
and 2/3 V
LCD
in case of 1/3 bias
• 1/4 V
LCD
, 2/4 V
LCD
and 3/4 V
LCD
in case of 1/4 bias
• only 1/2 V
LCD
in case of 1/2 bias.
LCD drive selection
Two resistive networks, one with low value resistors (R
L
) and one with high value resistors
(R
H
) are respectively used to increase the current during transitions and reduce power
consumption in static state.
The EN switch follows the rules described below (see Figure 75):
• If LCDEN bit in the LCD_CR register is set, the EN switch is closed.
• When clearing the LCDEN bit in the LCD_CR register, the EN switch is open at the end
of the even frame in order to avoid a medium voltage level different from 0 considering
the entire frame odd plus even.
The PON[2:0] (Pulse ON duration) bits in the LCD_FCR register configure the time during
which R
L
is enabled through the HD (high drive) switch when the levels of the common and
segment lines change (see Figure 75). A short drive time will lead to lower power
consumption, but displays with high internal resistance may need a longer drive time to
achieve satisfactory contrast.
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