Reset and clock control (RCC) RM0367
184/1043 RM0367 Rev 7
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock and the disabling of the HSE oscillator. If the HSE
oscillator clock is the clock entry of the PLL used as system clock when the failure occurs,
the PLL is disabled too.
When an HSE failure occurs, the system clock can be switched to the MSI or to the internal
16-MHz HSI clock depending on the value of STOPWUCK bit in the RCC_CFGR register.
7.2.11 LSE Clock Security System
Clock Security System can be activated on the LSE by software. This is done by writing the
CSSLSEON bit in the RCC_CSR register. This bit can be disabled by a hardware reset, an
RTC software reset, or after an LSE clock failure detection. CSSLSEON bit must be written
after the LSE and LSI clocks are enabled (LSEON and LSION set) and ready (LSERDY and
LSIRDY bits set by hardware), and after the RTC clock has been selected through the
RTCSEL bit.
The LSE CSS works in all modes: run, Sleep, Stop and Standby.
If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
to the RTC but the content of the registers does not change.
A wakeup is generated in Standby mode. In any other modes, an interrupt can be sent to
wake-up the software (see Section 7.3.5).
The software MUST then reset the CSSLSEON bit and stop the defective 32 kHz oscillator
by resetting LSEON bit. It can change the RTC clock source (LSI, HSE or no clock) through
the RTCSEL bit, or take any required action to secure the application.
The frequency of LSE oscillator must be higher than 30 kHz to avoid false positive CSS
detection.
7.2.12 RTC and LCD clock
The RTC and LCD have the same clock source which can be either the LSE, the LSI, or the
HSE 4 MHz clock (HSE divided by a programmable prescaler). It is selected by
programming the RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.21) and the
RTCPRE[1:0] bits in the RCC_CR register (see Section 7.3.1).
Once the RTC and LCD clock source have been selected, the only possible way of
modifying the selection is to set the RTCRST bit in the RCC_CSR register, or by a POR.
If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and
Standby low-power modes, and can be used as wakeup source. However, when the HSE is
the RTC clock source, the RTC cannot be used in the Stop and Standby low-power modes.
The LCD can however be used in the Stop low-power mode if the LSE or LSI is used as the
RTC clock source.
When the RTC is clocked by the LSE, the RTC remains clocked and functional under
system reset.
Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.
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