RM0367 Rev 7 837/1043
RM0367 Low-power universal asynchronous receiver transmitter (LPUART)
872
30.4.2 LPUART transmitter
The transmitter can send data words of either 7 or 8 or 9 bits depending on the M bits status.
The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The
data in the transmit shift register is output on the TX pin.
Character transmission
During an LPUART transmission, data shifts out least significant bit first (default
configuration) on the TX pin. In this mode, the LPUART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register (see Figure 242).
Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by LPUART: 1 and 2 stop bits.
Note: The TE bit must be set before writing the data to be transmitted to the LPUART_TDR.
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
• 1 stop bit: This is the default value of number of stop bits.
• 2 stop bits: This will be supported by normal LPUART, Single-wire and Modem
modes.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01)
or 9 low bits (when M[1:0] = 10) followed by 2 stop bits. It is not possible to transmit long
breaks (break of length greater than 9/10/11 low bits).
Figure 269. Configurable stop bits
MS31885V1
8-bit Word length (M[1:0]=00 bit is reset)
** LBCL bit controls last data clock pulse
Bit7Start bit
Stop
bit
Next
start
bit
Possible
parity bit
Data frame
Next data frame
CLOCK
**
a) 1 Stop bit
b) 2 Stop bits
Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Next data frame
Bit7Start bit
2
Stop
bits
Next
start
bit
Possible
parity bit
Data frame
Bit6Bit5Bit4Bit3Bit2Bit1Bit0