ST STM32L0x3 - Figure 165. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0 X6; Figure 166. Counter Timing Diagram, Internal Clock Divided by 2

RM0367 Rev 7 559/1043
RM0367 General-purpose timers (TIM21/22)
601
Figure 165. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
1. Here, center-aligned mode 1 is used (for more details refer to Section 22.4.1: TIM21/22 control register 1
(TIMx_CR1) on page 583).
Figure 166. Counter timing diagram, internal clock divided by 2
MS31189V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00020304
05
06
01
CEN
02 03 0401 05 0304
Counter underflow
MS31190V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0003
0002
0001
0000
0001
0002
0003