RM0367 Rev 7 851/1043
RM0367 Low-power universal asynchronous receiver transmitter (LPUART)
872
Figure 274. Reception using DMA
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the LPUART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
30.4.10 RS232 Hardware flow control and RS485 Driver Enable
using LPUART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 263 shows how to connect 2 devices in this mode:
Figure 275. Hardware flow control between 2 LPUARTs
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the LPUART_CR3 register).
MSv31891V3
TX line
Frame 1
F2
F3
Set by hardware
cleared by DMA read
F1
Frame 2
Frame 3
RXNE flag
LPUART_RDR
DMA request
DMA reads
LPUART_RDR
DMA TCIF flag
(transfer complete)
Set by hardware
Cleared by
software
Software configures
the DMA to receive 3
datablocks and
enables the LPUART
DMA reads F3
from
LPUART_RDR
DMA reads F2
from
LPUART_RDR
DMA reads F1
from
LPUART_RDR
DMA transfer is
complete
(TCIF=1 in
DMA_ISR)
MSv31892V2
TX circuit
LPUART 1
TX
RX circuit
RX circuit
LPUART 2
TX circuit
TX
CTS
CTS
RTS
RX
RTS
RX
To Next Page
Loading...
Need help?
General
