RM0367 Rev 7 155/1043
RM0367 Power control (PWR)
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6.3.2 Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 7.3.4: Clock configuration register (RCC_CFGR).
6.3.3 Peripheral clock gating
In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped
at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB peripheral clock enable register
(RCC_AHBENR), APB2 peripheral clock enable register (RCC_APB2ENR), APB1
peripheral clock enable register (RCC_APB1ENR) (see Section 7.3.13: AHB peripheral
clock enable register (RCC_AHBENR), Section 7.3.15: APB1 peripheral clock enable
register (RCC_APB1ENR) and Section 7.3.14: APB2 peripheral clock enable register
(RCC_APB2ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2).
6.3.4 Low-power run mode (LP run)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
f_MSI range1.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.
Low-power run mode can only be entered when V
CORE
is in range 2. In addition, the
dynamic voltage scaling must not be used when Low-power run mode is selected. Only Stop
and Sleep modes with regulator configured in low-power mode is allowed when Low-power
run mode is selected.
Note: In Low-power run mode, all I/O pins keep the same state as in Run mode.
Entering Low-power run mode
To enter Low-power run mode proceed as follows:
1. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and
RCC_AHBENR registers.
2. The frequency of the system clock must be decreased to not exceed the frequency of
f_MSI range1.
3. The regulator is forced in low-power mode by software (LPRUN and LPSDSR bits set)
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