ST STM32L0x3 User Manual

Basic timers (TIM6/7) RM0367
608/1043 RM0367 Rev 7
Figure 198. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
23.3.3 Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 199 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
MS31083V2
F5
36
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00
02
03 04 05
06
07F1
F2
F3 F4
F5F0
01
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
Auto-reload shadow
register
F5
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ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English