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Touch sensing controller (TSC) RM0367

426/1043 RM0367 Rev 7

18.6.3 TSC interrupt clear register (TSC_ICR)

Address offset: 0x08

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEIC EOAIC

rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 MCEIC: Max count error interrupt clear

This bit is set by software to clear the max count error flag and it is cleared by hardware

when the flag is reset. Writing a ‘0’ has no effect.

0: No effect

1: Clears the corresponding MCEF of the TSC_ISR register

Bit 0 EOAIC: End of acquisition interrupt clear

This bit is set by software to clear the end of acquisition flag and it is cleared by hardware

when the flag is reset. Writing a ‘0’ has no effect.

0: No effect

1: Clears the corresponding EOAF of the TSC_ISR register

ST STM32L0x3 User Manual

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