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RM0367 Rev 7 589/1043

RM0367 General-purpose timers (TIM21/22)

601

22.4.4 TIM21/22 Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

22.4.5 TIM21/22 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. TIE Res. Res. Res. CC2IE CC1IE UIE

rw rw rw rw

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TIE: Trigger interrupt enable

0: Trigger interrupt disabled.

1: Trigger interrupt enabled.

Bits 5:3 Reserved, must be kept at reset value.

Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled.

1: CC2 interrupt enabled.

Bit 1 CC1IE: Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled.

1: CC1 interrupt enabled.

Bit 0 UIE: Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

1514131211109876543210

Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. TIF Res. Res. Res. CC2IF CC1IF UIF

rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 CC2OF: Capture/compare 2 overcapture flag

refer to CC1OF description

Bit 9 CC1OF: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input

capture mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was

already set

Bits 8:7 Reserved, must be kept at reset value.

ST STM32L0x3 User Manual

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