RM0367 Rev 7 279/1043
RM0367 Direct memory access controller (DMA)
288
11.6.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.
Bit 2 HTIF1: half transfer (HT) flag for channel 1
0: no HT event
1: a HT event occurred
Bit 1 TCIF1: transfer complete (TC) flag for channel 1
0: no TC event
1: a TC event occurred
Bit 0 GIF1: global interrupt flag for channel 1
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res.
CTEIF7
CHTIF7
CTCIF7
CGIF7
CTEIF6
CHTIF6
CTCIF6
CGIF6
CTEIF5
CHTIF5
CTCIF5
CGIF5
wwwwwwwwwwww
1514131211109876543210
CTEIF4
CHTIF4
CTCIF4
CGIF4
CTEIF3
CHTIF3
CTCIF3
CGIF3
CTEIF2
CHTIF2
CTCIF2
CGIF2
CTEIF1
CHTIF1
CTCIF1
CGIF1
wwwwww w w w w w w w w w w
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 CTEIF7: transfer error flag clear for channel 7
Bit 26 CHTIF7: half transfer flag clear for channel 7
Bit 25 CTCIF7: transfer complete flag clear for channel 7
Bit 24 CGIF7: global interrupt flag clear for channel 7
Bit 23 CTEIF6: transfer error flag clear for channel 6
Bit 22 CHTIF6: half transfer flag clear for channel 6
Bit 21 CTCIF6: transfer complete flag clear for channel 6
Bit 20 CGIF6: global interrupt flag clear for channel 6
Bit 19 CTEIF5: transfer error flag clear for channel 5
Bit 18 CHTIF5: half transfer flag clear for channel 5
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