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RM0367 Rev 7 257/1043

RM0367 System configuration controller (SYSCFG)

264

Bit 3 UFB: User bank swapping

This bit is available only on category 5 devices and reserved on other categories.

It is set and cleared by software. It controls the Bank 1/2 mapping (see Ta ble 8: NV M

organization for UFB = 0 (128 Kbyte category 5 devices) and Table 10: NVM organization

for UFB = 0 (64 Kbyte category 5 devices)).

0: Flash Program memory Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if

MEM_MODE=00) and Data EEPROM Bank 1 at 0x0808 0000 (aliased at 0x0008 0000 if

MEM_MODE=00)

1: Flash Program memory Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if

MEM_MODE=00) and Data EEPROM Bank 2 at 0x0808 0000 (and aliased at 0x0008 0000

if MEM_MODE=00)

Bit 2 Reserved, must be kept at reset value

Bits 1:0 MEM_MODE: Memory mapping selection bits

These bits are set and cleared by software. This bit controls the memory’s internal mapping

at address 0x0000 0000. After reset these bits take on the memory mapping selected by the

BOOT pins (see Section 2.4: Boot configuration on page 64).

00: Main Flash memory mapped at 0x0000 0000

01: System Flash memory mapped at 0x0000 0000

10: reserved

11: SRAM mapped at 0x0000 0000.

ST STM32L0x3 User Manual

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