Power control (PWR) RM0367
168/1043 RM0367 Rev 7
Bit 10 FWU: Fast wakeup
This bit works in conjunction with ULP bit.
If ULP = 0, FWU is ignored
If ULP = 1 and FWU = 1: V
REFINT
startup time is ignored when exiting from low-power mode.
The VREFINTRDYF flag in the PWR_CSR register indicates when the V
REFINT
is ready
again.
If ULP=1 and FWU = 0: Exiting from low-power mode occurs only when the V
REFINT
is ready
(after its startup time). This bit is not reset by resetting the PWRRST bit in the
RCC_APB1RSTR register.
0: Low-power modes exit occurs only when V
REFINT
is ready
1: V
REFINT
start up time is ignored when exiting low-power modes
Bit 9 ULP: Ultra-low-power mode
When set, the V
REFINT
is switched off in low-power mode. The BOR, PVD, and temperature
sensor also rely on the voltage reference. This bit is not reset by resetting the PWRRST bit
in the RCC_APB1RSTR register. When this bit is set, the LCDEN bit of register LCD_CR
must not be set.
0: V
REFINT
is on in low-power mode
1: V
REFINT
is off in low-power mode
Bit 8 DBP: Disable backup write protection
In reset state, the RTC, RTC backup registers and RCC CSR register are protected against
parasitic write access. This bit must be set to enable write access to these registers.
0: Access to RTC, RTC Backup and RCC CSR registers disabled
1: Access to RTC, RTC Backup and RCC CSR registers enabled
Note: If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, this bit must remain set
to 1.
The DBP bit must remain set while LCD is in use.
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the
programmable voltage detector:
000: 1.9 V
001: 2.1 V
010: 2.3 V
011: 2.5 V
100: 2.7 V
101: 2.9 V
110: 3.1 V
111: External input analog voltage (Compare internally to V
REFINT
)
PVD_IN input (PB7) has to be configured as analog input when PLS[2:0] = 111.
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Programmable voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby flag (write).
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