RM0367 Rev 7 169/1043
RM0367 Power control (PWR)
172
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup flag after 2 system clock cycles
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software.
0: Enter Stop mode when the CPU enters Deepsleep.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPSDSR: Low-power deepsleep/Sleep/Low-power run
– DeepSleep/Sleep modes
When this bit is set, the regulator switches in low-power mode when the CPU enters sleep
or Deepsleep mode. The regulator goes back to Main mode when the CPU exits from
these modes.
– Low-power run mode
When this bit is set, the regulator switches in low-power mode when the bit LPRUN is set.
The regulator goes back to Main mode when the bit LPRUN is reset.
This bit is set and cleared by software.
0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode
1: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode
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