ST STM32L0x3 User Manual

Reset and clock control (RCC) RM0367
216/1043 RM0367 Rev 7
Bit 28 PWRSMEN: Power interface clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Power interface clock disabled in Sleep mode
1: Power interface clock enabled in Sleep mode (if enabled by PWREN)
Bit 27 CRSSMEN: Clock recovery system clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Clock recovery system clock disabled in Sleep mode
1: Clock recovery system clock enabled in Sleep mode (if enabled by CRSEN)
Bits 26:24 Reserved, must be kept at reset value.
Bit 23 USBSMEN: USB clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USB clock disabled in Sleep mode
1: USB clock enabled in Sleep mode (if enabled by USBEN)
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: I2C2 clock disabled in Sleep mode
1: I2C2 clock enabled in Sleep mode (if enabled by I2C2EN)
Bit 21 I2C1SMEN: I2C1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: I2C1 clock disabled in Sleep mode
1: I2C1 clock enabled in Sleep mode (if enabled by I2C1EN)
Bit 20 USART5SMEN: USART5 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART5 clock disabled in Sleep mode
1: USART5 clock enabled in Sleep mode (if enabled by USART5EN)
Bit 19 USART4SMEN: USART4 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART4 clock disabled in Sleep mode
1: USART4 clock enabled in Sleep mode (if enabled by USART4EN)
Bit 18 LPUART1SMEN: LPUART1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: LPUART1 clock disabled in Sleep mode
1: LPUART1 clock enabled in Sleep mode (if enabled by LPUART1EN)
Bit 17 USART2SMEN: USART2 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART2 clock disabled in Sleep mode
1: USART2 clock enabled in Sleep mode (if enabled by USART2EN)
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2SMEN: SPI2 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: SPI2 clock disabled in Sleep mode
1: SPI2 clock enabled in Sleep mode (if enabled by SPI2SEN)
Bits 13:12 Reserved, must be kept at reset value.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English