RM0367 Rev 7 109/1043
RM0367 Flash program memory and data EEPROM (FLASH)
122
Bits 31:24 Reserved, must be kept at reset value
Bit 23 NZDISABLE: Non-Zero check notification disable
When this bit is set, the application software does not check if the previous NVM content is
zero before programming a word or an half-page in the program or boot area. As a result,
the NOTZEROERR flag will always remain at 0 and no interrupt will be generated if the
above condition is met. By default, NZDISABLE is set to 0. It can be modified only when
PELOCK is 0.
0: error interrupt disabled
1: error interrupt enabled
On category 3 devices, this bit is not available and the behavior corresponds to
NZDISABLE=0.
Bits 22:19 Reserved, must be kept at reset value
Bit 18 OBL_LAUNCH
Setting this bit, the software requests the reloading of Option byte. The Option byte reloading
does not stop an ongoing modify operation, but it blocks new ones. The Option byte reloading
generates a system reset.
0: Option byte loading completed.
1: Option byte loading to be done.
Note: This bit can only be modified when OPTLOCK is 0. Locking OPTLOCK (or other lock
bits) does not reset this bit.
Bit 17 ERRIE: Error interrupt enable
0: Error interrupt disable.
1: Error interrupt enable.
Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this
bit; the interrupt remains enabled.
Bit 16 EOPIE: End of programming interrupt enable
0: End of program interrupt disable.
1: End of program interrupt enable.
Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this
bit; the interrupt remains enabled.
Bit 15 PARALLELBANK: Parallel bank programming mode.
This bit can be set and cleared by software when no program or erase operation is ongoing.
When it is set, 2 half-pages can be programmed, the first one in Bank 1 and the second one
in Bank 2.
0: Parallel bank mode disabled
1: Parallel bank mode enabled
This bit is available only for category 5 devices.
Bits 14:11 Reserved, must be kept at reset value
Bit 10 FPRG: Half Page programming mode
0: Half Page programming disabled.
1: Half Page programming enabled.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
Bit 9 ERASE
0: No erase operation requested.
1: Erase operation requested.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
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