Inter-integrated circuit (I2C) interface RM0367
760/1043 RM0367 Rev 7
28.7.9 I2C PEC register (I2C_PECR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: No wait states
Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 28.3: I2C implementation.
Bit 10 OVRCF: Overrun/Underrun flag clear
Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
Bit 9 ARLOCF: Arbitration lost flag clear
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
Bit 8 BERRCF: Bus error flag clear
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: STOP detection flag clear
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
Bit 4 NACKCF: Not Acknowledge flag clear
Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
Bit 3 ADDRCF: Address matched flag clear
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also
clears the START bit in the I2C_CR2 register.
Bits 2:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. PEC[7:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PEC[7:0]: Packet error checking register
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE=0.
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