RM0367 Rev 7 291/1043
RM0367 Nested vectored interrupt controller (NVIC)
301
29 36 settable
LPUART1 + AES
+RNG
LPUART1 global interrupt through
EXTI28 + AES global interrupt +
RNG global interrupt
0x0000_00B4
30 37 settable LCD LCD global interrupt 0x0000_00B8
31 38 settable USB USB event interrupt through EXTI18 0x0000_00BC
1. The grayed cells correspond to the Cortex
®
-M0+ interrupts.
2. Refer to Table 1: STM32L0x3 memory density, to Table 2: Overview of features per category and to the device datasheets
for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or
peripherals are reserved.
Table 55. List of vectors
(1)(2)
(continued)
Position Priority
Type of
priority
Acronym Description Address
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