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General-purpose timers (TIM21/22) RM0367

568/1043 RM0367 Rev 7

detected (sampled at f

DTS

frequency). Then write IC1F bits to ‘0011’ in the

TIMx_CCMR1 register.

3. Select the edge of the active transition on the TI1 channel by programming CC1P and

CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).

4. Program the input prescaler. In our example, we wish the capture to be performed at

each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the

TIMx_CCMR1 register).

5. Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

6. If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register.

For code example, refer to A.11.3: Input capture configuration code example.

When an input capture occurs:

• The TIMx_CCR1 register gets the value of the counter on the active transition.

• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures

occurred whereas the flag was not cleared.

• An interrupt is generated depending on the CC1IE bit.

For code example, refer to A.11.4: Input capture data management code example.

In order to handle the overcapture, it is recommended to read the data before the

overcapture flag. This is to avoid missing an overcapture which could happen after reading

the flag and before reading the data.

Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in

the TIMx_EGR register.

ST STM32L0x3 User Manual

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