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RM0367 Rev 7 745/1043

RM0367 Inter-integrated circuit (I2C) interface

763

When a timeout violation is detected in master mode, a STOP condition is automatically

sent.

When a timeout violation is detected in slave mode, SDA and SCL lines are automatically

released.

When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an

interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Alert (ALERT)

This section is relevant only when the SMBus feature is supported. Refer to Section 28.3:

I2C implementation.

The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the

alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin.

An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

28.4.18 DMA requests

Transmission using DMA

DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit

in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA

peripheral (see Section 11: Direct memory access controller (DMA) on page 265) to the

I2C_TXDR register whenever the TXIS bit is set.

Only the data are transferred with DMA.

• In master mode: the initialization, the slave address, direction, number of bytes and

START bit are programmed by software (the transmitted slave address cannot be

transferred with DMA). When all data are transferred using DMA, the DMA must be

initialized before setting the START bit. The end of transfer is managed with the

NBYTES counter. Refer to Master transmitter on page 721.

For code example refer to A.16.8: I2C configured in master mode to transmit with DMA code

example.

• In slave mode:

– With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be

initialized before the address match event, or in ADDR interrupt subroutine, before

clearing ADDR.

– With NOSTRETCH=1, the DMA must be initialized before the address match

event.

• For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.

Refer to SMBus slave transmitter on page 735 and SMBus master transmitter on

page 739.

Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

ST STM32L0x3 User Manual

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