Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367
776/1043 RM0367 Rev 7
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
• The ORE bit is set.
• The RDR content will not be lost. The previous data is available when a read to
USART_RDR is performed.
• The shift register will be overwritten. After that point, any data received during overrun
is lost.
• An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.
• The ORE bit is reset by setting the ORECF bit in the ICR register.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received.
Selecting the proper oversampling method
When the dual clock domain with the wakeup from Stop mode is supported, the clock
source can be one of the following sources: PCLK (default), LSE, HSI16 or SYSCLK.
Otherwise, the USART clock source is PCLK.
Choosing LSE or HSI16 as clock source may allow the USART to receive data while the
MCU is in low-power mode. Depending on the received data and wakeup mode selection,
the USART wakes up the MCU, when needed, in order to transfer the received data by
software reading the USART_RDR register or by DMA.
For the other clock sources, the system must be active in order to allow USART
communication.
The receiver implements different user-configurable oversampling techniques for data
recovery by discriminating between valid incoming data and noise. This allows a trade-off
between the maximum communication speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 247 and
Figure 248).
Depending on the application:
• Select oversampling by 8 (OVER8=1) to achieve higher speed (up to f
CK
/8). In this
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 29.5.5: Tolerance of the USART receiver to clock deviation on page 781)
• Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to
clock deviations. In this case, the maximum speed is limited to maximum f
CK
/16 where
f
CK
is the clock source frequency.
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