Low-power universal asynchronous receiver transmitter (LPUART) RM0367
842/1043 RM0367 Rev 7
Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
• The FE bit is set by hardware.
• The invalid data is transferred from the Shift register to the LPUART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
LPUART_CR3 register.
The FE bit is reset by writing 1 to the FECF in the LPUART_ICR register.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode.
• 1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
• 2 stop bits: Sampling for the 2 stop bits is done in the middle of the second stop bit.
The RXNE and FE flags are set just after this sample i.e. during the second stop bit.
The first stop bit is not checked for framing error.
30.4.4 LPUART baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the LPUART_BRR register.
LPUARTDIV is coded on the LPUART_BRR register.
Note: The baud counters are updated to the new value in the baud registers after a write operation
to LPUART_BRR. Hence the baud rate register value should not be changed during
communication.
It is forbidden to write values less than 0x300 in the LPUART_BRR register.
fck must be in the range [3 x baud rate, 4096 x baud rate].
The maximum baud rate that can be reached when the LPUART clock source is the LSE, is
9600 baud. Higher baud rates can be reached when the LPUART is clocked by clock
sources different than the LSE clock. For example, if the USART clock source is the system
clock (maximum is 32 MHz), the maximum baud rate that can be reached is 10 Mbaud.
Tx/Rx baud
256 f×
CK
LPUARTDIV
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