RM0367 Rev 7 845/1043
RM0367 Low-power universal asynchronous receiver transmitter (LPUART)
872
Note: The data specified in Table 151 may slightly differ in the special case when the received
frames contain some Idle frames of exactly 10-bit durations when M bits = 00 (11-bit
durations when M bits =01 or 9- bit durations when M bits = 10).
30.4.6 Multiprocessor communication using LPUART
It is possible to perform multiprocessor communication with the LPUART (with several
LPUARTs connected in a network). For instance one of the LPUARTs can be the master, its
TX output connected to the RX inputs of the other LPUARTs. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant
LPUART service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In order to use the mute mode feature, the MME bit must be set in the LPUART_CR1
register.
In mute mode:
• None of the reception status bits can be set.
• All the receive interrupts are inhibited.
• The RWU bit in LPUART_ISR register is set to 1. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the LPUART_RQR register,
under certain conditions.
The LPUART can enter or exit from mute mode using one of two methods, depending on
the WAKE bit in the LPUART_CR1 register:
• Idle Line detection if the WAKE bit is reset,
• Address Mark detection if the WAKE bit is set.
Idle line detection (WAKE=0)
The LPUART enters mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the LPUART_ISR register. An example of mute mode behavior
using Idle line detection is given in Figure 249.
8 bits (M=00), 2 stop bit 2.08% 2.86% 4.35% 4.42%
9 bits (M=01), 2 stop bit 1.82% 2.56% 3.90% 4.42%
7 bits (M=10), 2stop bit 2.34% 3.23% 4.92% 4.42%
Table 151. Tolerance of the LPUART receiver (continued)
M bits 768 ≤ BRR <1024 1024 ≤ BRR < 2048 2048 ≤ BRR < 4096 4096 ≤ BRR
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