RM0367 Rev 7 871/1043
RM0367 Low-power universal asynchronous receiver transmitter (LPUART)
872
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 242).
When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
Note: This register must be written only when TXE=1.
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