RM0367 Rev 7 951/1043
RM0367 Universal serial bus full-speed device interface (USB)
955
32.6.2 Buffer descriptor table
Note: The buffer descriptor table is located inside the packet buffer memory in the separate "USB
SRAM" address space.
Although the buffer descriptor table is located inside the packet buffer memory ("USB
SRAM" area), its entries can be considered as additional registers used to configure the
location and size of the packet buffers used to exchange data between the USB macro cell
and the device.
The first packet memory location is located at USB SRAM base address. The buffer
descriptor table entry associated with the USB_EPnR registers is described below. The
packet memory should be accessed only by byte (8-bit) or half-word (16-bit) accesses.
Word (32-bit) accesses are not allowed.
A thorough explanation of packet buffers and the buffer descriptor table usage can be found
in Structure and usage of packet buffers on page 927.
Transmission buffer address n (USB_ADDRn_TX)
Address offset: [USB_BTABLE] + n*8
Note: In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_ADDRn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_ADDRn_RX_0.
Transmission byte count n (USB_COUNTn_TX)
Address offset: [USB_BTABLE] + n*8 + 2
Note: In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_COUNTn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_COUNTn_RX_0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRn_TX[15:1] -
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw -
Bits 15:1 ADDRn_TX[15:1]: Transmission buffer address
These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
Bit 0 Must always be written as ‘0 since packet memory is half-word wide and all packet buffers
must be half-word aligned.
151413121110987654321 0
Res. Res. Res. Res. Res. Res. COUNTn_TX[9:0]
rw rw rw rw rw rw rw rw rw rw
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