Revision history RM0367
1024/1043 RM0367 Rev 7
04-May-2015
3
(continued)
RCC
Updated ADC clock in Section 7.2: Clocks. Added HSE failure in
Section 7.2.10: HSE clock security system (CSS).
Added HSI48DIV6EN and updated HSI48DIV6EN in Section 7.3.3:
Clock recovery RC register (RCC_CRRCR).
Section 7.3.7: Clock interrupt clear register (RCC_CICR): changed all
bit access type to ‘w, renamed USB bit into UFB and bit moved to bit
3.
Renamed TOUCHEN into TSCEN in Section 7.3.13: AHB peripheral
clock enable register (RCC_AHBENR).
Renamed MIFIEN into FWEN and description updated in Section
7.3.14: APB2 peripheral clock enable register (RCC_APB2ENR).
Updated Section 7.3.21: Control/status register (RCC_CSR).
Added IOPERST in Section 7.3.8: GPIO reset register
(RCC_IOPRSTR), IOPEENR in Section 7.3.12: GPIO clock enable
register (RCC_IOPENR), and IOPESMEN in Section 7.3.16: GPIO
clock enable in Sleep mode register (RCC_IOPSMENR).
Section 7.3.11: APB1 peripheral reset register (RCC_APB1RSTR):
Added USART4RST, USART5RST, TIM3RST, TIM7RST and
I2C3RST. Renamed UARTxRST bits into USARTxRST.
Section 7.3.15: APB1 peripheral clock enable register
(RCC_APB1ENR): Added USART4EN, USART5EN, TIM3EN and
TIM7EN and I2C3EN. Renamed UARTxEN bits into USARTxEN.
Section 7.3.19: APB1 peripheral clock enable in Sleep mode register
(RCC_APB1SMENR): Added USART4SMEN, USART5SMEN,
TIM3SMEN, TIM7SMEN and I2C3SMEN. Renamed UARTxSMEN
bits into USARTxSMEN.
Added I2C3SEL bits in Section 7.3.20: Clock configuration register
(RCC_CCIPR).
CRS:
Added note related to SYNCSRC[1:0] in Section 8.6.2: CRS
configuration register (CRS_CFGR) register.
GPIOs
Add Port E for category 5 devices.
Table 181. Document revision history (continued)
Date Revision Changes
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