ST STM32L0x3 User Manual

RM0367 Rev 7 117/1043
RM0367 Flash program memory and data EEPROM (FLASH)
122
Bit 20 WDG_SW
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
0: Hardware watchdog.
1: Software watchdog.
Bits 19:16 BOR_LEV: Brownout reset threshold level
These bits reset the threshold level for a 1.45 V to 1.55 V voltage range (power-down only). In
this particular case, V
DD
must have been above V
BOR0
to start the device OBL sequence, in
order to disable the BOR. The power-down is then monitored by the PDR. If the BOR is
disabled, a “grey zone” exists between 1.65 V and the VPDR threshold (this means V
DD
can
be below the minimum operating voltage (1.65 V) without any reset until the VPDR threshold).
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with
0x8.
0xxx: BOR OFF. This is the reset threshold level for the 1.45 V - 1.55 V voltage range
(power-down only).
In this particular case, V
DD
must have been above BOR LEVEL 1 to start the device OBL
sequence in order to disable the BOR. The power-down is then monitored by the PDR.
Note: If the BOR is disabled, a "grey zone" exists between 1.65 V and the VPDR threshold
(this means that V
DD
may be below the minimum operating voltage (1.65 V) without
causing a reset until it crosses the VPDR threshold)
1000: BOR LEVEL 1 is the reset threshold level for V
BOR0
(around 1.8 V)
1001: BOR LEVEL 2 is the reset threshold level for V
BOR1
(around 2.0 V)
1010: BOR LEVEL 3 is the reset threshold level for V
BOR2
(around 2.5 V)
1011: BOR LEVEL 4 is the reset threshold level for V
BOR3
(around 2.7 V).
1100: BOR LEVEL 5 is the reset threshold level for V
BOR4
(around 3.0 V)
Note: Refer to the device datasheets for the exact definition of BOR levels.
Bits 15:9 Reserved, must be kept at reset value
Bit 8 WPRMOD
This bit selects between write and read protection of Flash program memory sectors. If there is
a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
0: PCROP disabled. The WRPROT bits are used as a write protection on a sector.
1: PCROP enabled. The WRPROT bits are used as a read protection on a sector.
Bits 7:0 RDPROT: Read protection
These bits contain the protection level loaded during the Option byte loading. If there is a
mismatch on this configuration during the Option bytes loading, it is loaded with 0x00.
0xAA: Level 0
0xCC: Level 2
Others: Level 1

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English