Reset and clock control (RCC) RM0367
188/1043 RM0367 Rev 7
Bit 18 HSEBYP: HSE clock bypass bit
This bit is set and cleared by software to bypass the oscillator with an external clock. The
external clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled. This bit is reset by
power-on reset. Its value is not modified by system reset
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
This bit is set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is
cleared, HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable bit
This bit is set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MSIRDY: MSI clock ready flag
This bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
Bit 8 MSION: MSI clock enable bit
This bit is set and cleared by software.
Set by hardware to force the MSI oscillator ON when exiting from Stop or Standby mode, or
in case of a failure of the HSE oscillator used directly or indirectly as system clock. This bit
cannot be cleared if the MSI is used as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 HSI16OUTEN: 16 MHz high-speed internal clock output enable
This bit is set and cleared by software. When this bit is set, TIM2 ETR input is connected to
the 16 MHz HSI output clock (HSI16) provided ETR_RMP is set to 011 in TIM2 option
register (TIM2_OR). This bit can be written anytime by the application.
0: HSI16 output clock disabled
1: HSI16 output clock enabled
Bit 4 HSI16DIVF HSI16 divider flag
This bit is set and reset by hardware. As a write in HSI16DIVEN has not an immediate effect
on the frequency, this flag indicates the current status of the HSI16 divider.
0: 16 MHz HSI clock not divided
1: 16 MHz HSI clock divided by 4
Bit 3 HSI16DIVEN HSI16 divider enable bit
This bit is set and reset by software to enable/disable the 16 MHz HSI divider by 4. It can be
written anytime.
0: no 16 MHz HSI division requested
1: 16 MHz HSI division by 4 requested
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