Reset and clock control (RCC) RM0367
222/1043 RM0367 Rev 7
Bits 7:3 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready bit
This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the
LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
This bit is reset by system reset.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable bit
This bit is set and cleared by software.
It is reset by system reset.
0: LSI oscillator OFF
1: LSI oscillator ON
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