Comparator (COMP) RM0367
382/1043 RM0367 Rev 7
Bit 13 COMP2LPTIMIN1: Comparator 2 LPTIM input 1 propagation bit
This bit is set and cleared by software (assuming COMP2LOCK not set). It sends
COMP2VALUE to LPTIM input 1.
0: Comparator 2 output gated
1: Comparator 2 output sent to LPTIM input 1
Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’.
Bit 12 COMP2LPTIMIN2: Comparator 2 LPTIM input 2 propagation bit
This bit is set and cleared by software (assuming COMP2LOCK not set). It sends
COMP2VALUE to LPTIM input 2.
0: Comparator 2 output gated
1: Comparator 2 output sent to LPTIM input 2
Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’.
Bit 11 Reserved, must be kept at reset value
Bits 10:8 COMP2INPSEL: Comparator 2 Input Plus connection configuration bit
These bits are set and cleared by software (only if COMP2LOCK not set). They select which
input is connected with the Input Plus of comparator 2
000: PA3
001: PB4
010: PB5
011: PB6
100: PB7
Others: Reserved.
Bit 7 Reserved, must be kept at reset value
Bits 6:4 COMP2INNSEL: Comparator 2 Input Minus connection configuration bit
These bits are set and cleared by software (only if COMP2LOCK not set). They select which
input is connected with the Input Minus of comparator 2.
000: VREFINT
001: PA2
010: DAC /PA4
011: DAC2/PA5
100: 1/4 VREFINT
101: 1/2 VREFINT
110: 3/4 VREFINT
111: PB3
Note: If VREFINT or a fraction of VREFINT (using the scaler) is selected, then EN_VREFINT
bit must be set in the SYSCFG_CFGR3 register (see Section 10.2.3: Reference
control and status register (SYSCFG_CFGR3)).
Bit 3 COMP2SPEED: Comparator 2 power mode selection bit
This bit is set and cleared by software (only if COMP2LOCK not set). It selects comparator
2 power mode.
0: slow speed
1: fast speed
Bits 2:1 Reserved, must be kept at reset value
Bit 0 COMP2EN: Comparator 2 enable bit
This bit is set and cleared by software (only if COMP2LOCK not set). It switches
oncomparator2.
0: Comparator 2 switched off.
1: Comparator 2 switched ON.